Dynamic voltage scaling for commercial FPGAs

Proceedings - 2005 IEEE International Conference on Field Programmable Technology

Volumn 2005, Issue , 2005, Pages 173-180

  Chow, C T ^a   Tsui, L S M ^a   Leong, P H W ^a,b   Luk, W ^a,b   Wilton, S J E ^c  

^a CHINESE UNIVERSITY OF HONG KONG   (Hong Kong)

^b IMPERIAL COLLEGE LONDON   (United Kingdom)

^c UNIVERSITY OF BRITISH COLUMBIA   (Canada)

Author keywords

[No Author keywords available]

Indexed keywords

CLOCK FREQUENCIES; DYNAMIC VOLTAGE SCALING (DVS); LOGIC DELAY MEASUREMENT CIRCUIT (LDMC); OPERATING CIRCUITS; CHIP TEMPERATURE; CLOSED-LOOP CONTROL; CONTROL SCHEMES; CRITICAL PATHS; DELAY MEASUREMENTS; LOGIC DELAYS; MEASUREMENT CIRCUIT; OPERATING CONDITION; RUNTIMES; SAFETY MARGIN;

AUTOMATION; CLOSED LOOP CONTROL SYSTEMS; CRITICAL PATH ANALYSIS; DELAY CIRCUITS; ROBUSTNESS (CONTROL SYSTEMS); VOLTAGE CONTROL; VOLTAGE SCALING;

FIELD PROGRAMMABLE GATE ARRAYS; FIELD PROGRAMMABLE GATE ARRAYS (FPGA);

EID: 33745993315     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/FPT.2005.1568543     Document Type: Conference Paper

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