Power-dissipation driven FPGA place and route under timing constraints

IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications

Volumn 46, Issue 5, 1999, Pages 634-637

  Roy, Kaushik ^a  

^a PURDUE UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; CAPACITANCE; CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; ELECTRIC LOADS; ELECTRIC LOSSES; ELECTRIC RESISTANCE; LEAKAGE CURRENTS; SHORT CIRCUIT CURRENTS;

LOGIC MODULES; LOW POWER DISSIPATION; PLACEMENT; ROUTING;

FIELD PROGRAMMABLE GATE ARRAYS;

EID: 0032627268     PISSN: 10577122     EISSN: None     Source Type: Journal    
DOI: 10.1109/81.762929     Document Type: Article

References (8)

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3. T.-L. Chou, K. Roy, and S. Prasad, "Estimation of circuit activity using signal correlations and simultaneous switching," in Proc. Int. Conf. Computer-Aided Design (ICCAD-94). 1994, to be published.
4. A. Chandrakashan, S. Sheng, and R. Brodersen, "Low power CMOS digital design," IEEE J. Solid-State Circuits, pp. 473-484, Apr. 1992.
5. A. El Gammal, J. Greene, J. Reyneri, E. Rogoyski, and A. Mohsen, "An architecture for electrically configurable gate array," IEEE J. Solid State Circuits, vol. 24, pp. 394-397, Apr. 1989.
6. K. Roy, "A bounded search algorithm for segmented channel routing for FPGA's and associated channel architecture issues," IEEE Trans. Computer-Aided-Design, pp. 1695-1705, Nov. 1993.
7. W. Elmore, "The transient response of damped linear networks with particular regard to wideband amplifiers," J. Appl. Phys., pp. 55-63, Jan. 1948.
8. Field Programmable Gate Array - Application Handbook, Texas Instruments, 1992.