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Volumn , Issue , 2002, Pages 211-218

Power-aware technology mapping for LUT-based FPGAs

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER CIRCUITS; CONFORMAL MAPPING; MAPPING; POWER MANAGEMENT; POWER MANAGEMENT (TELECOMMUNICATION); RECONFIGURABLE HARDWARE;

EID: 84962890444     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/FPT.2002.1188684     Document Type: Conference Paper
Times cited : (48)

References (18)
  • 4
    • 0028259317 scopus 로고
    • FlowMap: An Optimal Technology Mapping Algorithm for Delay Optimization in Lookup-Table Based FPGA Designs
    • J. Cong and Y. Ding, "FlowMap: An Optimal Technology Mapping Algorithm for Delay Optimization in Lookup-Table Based FPGA Designs," IEEE Trans. on CAD, Vol. 13, No. 1, 1994, pp. 1-12.
    • (1994) IEEE Trans. on CAD , vol.13 , Issue.1 , pp. 1-12
    • Cong, J.1    Ding, Y.2
  • 5
    • 0028455029 scopus 로고
    • On Area/Depth Trade-off in LUT-Based FPGA Technology Mapping
    • J. Cong and Y. Ding, "On Area/Depth Trade-off in LUT-Based FPGA Technology Mapping," IEEE Trans. on VLSI Systems, Vol. 2, No. 2, 1994, pp. 137-148.
    • (1994) IEEE Trans. on VLSI Systems , vol.2 , Issue.2 , pp. 137-148
    • Cong, J.1    Ding, Y.2
  • 9
    • 84964426030 scopus 로고    scopus 로고
    • LUT-Based FPGA Technology Mapping for Power Minimization with Optimal Depth
    • H. Li, W-K. Mak and Srinivas Katkoori, "LUT-Based FPGA Technology Mapping for Power Minimization with Optimal Depth," IEEE Computer Society Workshop on VLSI. 2001, pp. 123-128.
    • (2001) IEEE Computer Society Workshop on VLSI , pp. 123-128
    • Li, H.1    Mak, W.-K.2    Katkoori, S.3
  • 11
    • 0030173035 scopus 로고    scopus 로고
    • Towards a High-Level Power Estimation Capability
    • M. Nemani and F. Najm, "Towards a High-Level Power Estimation Capability," IEEE Trans. on CAD, Vol. 15, No. 6, 1996, pp. 588-598.
    • (1996) IEEE Trans. on CAD , vol.15 , Issue.6 , pp. 588-598
    • Nemani, M.1    Najm, F.2
  • 12
    • 0032681920 scopus 로고    scopus 로고
    • Cut Ranking and Pruning: Enabling A General And Efficient FPGA Mapping Solution
    • J. Cong, C. Wu and E. Ding, "Cut Ranking and Pruning: Enabling A General And Efficient FPGA Mapping Solution," ACM Int. Symp. on FPGAs, 1999, pp. 29-35.
    • (1999) ACM Int. Symp. on FPGAs , pp. 29-35
    • Cong, J.1    Wu, C.2    Ding, E.3
  • 13
    • 0028341924 scopus 로고
    • Routability-Driven Technology Mapping for Lookup Table-Based FPGAs
    • M. Schlag, J. Kong and P.K. Chan, "Routability-Driven Technology Mapping for Lookup Table-Based FPGAs," IEEE Trans. on CAD, Vol. 13, No. 1, 1994, pp. 13-26.
    • (1994) IEEE Trans. on CAD , vol.13 , Issue.1 , pp. 13-26
    • Schlag, M.1    Kong, J.2    Chan, P.K.3
  • 14
    • 0003934798 scopus 로고
    • UC Berkeley, Memorandum No. UCB/ERL M92/41, Electronics Research Laboratory, May
    • E.M. Sentovich et al., "SIS: A System for Sequential Circuit Synthesis," UC Berkeley, Memorandum No. UCB/ERL M92/41, Electronics Research Laboratory, May 1992.
    • (1992) SIS: A System for Sequential Circuit Synthesis
    • Sentovich, E.M.1
  • 15
    • 84948591324 scopus 로고
    • DAG-Map: Graph-Based FPGA Technology Mapping for Delay Optimization
    • September
    • K.C. Chen et al., "DAG-Map: Graph-Based FPGA Technology Mapping for Delay Optimization," IEEE Design and Test of Computers, September 1992, pp. 7-20.
    • (1992) IEEE Design and Test of Computers , pp. 7-20
    • Chen, K.C.1
  • 18
    • 84962920301 scopus 로고    scopus 로고
    • TSMC 0.18μm process, TSMC Corp., 2002, http://www.tsmc.com/english/technology/t0103-htm.
    • (2002) TSMC 0.18μm Process


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.