A dynamically-reconfigurable, power-efficient turbo decoder

Proceedings - 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, FCCM 2004

Volumn , Issue , 2004, Pages 91-100

  Liang, Jian ^a   Tessier, Russell ^a   Goeckel, Dennis ^a  

^a University of Massachusetts   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

HARDWARE DECODERS; INFORMATION TRANSFERS; POWER-CONSTRAINED SYSTEMS; SHANNON LIMITS;

ALGORITHMS; BIT ERROR RATE; COMMUNICATION SYSTEMS; COMPUTATIONAL COMPLEXITY; COMPUTER HARDWARE; COMPUTER SIMULATION; ELECTRIC POWER UTILIZATION; FIELD PROGRAMMABLE GATE ARRAYS; FLIP FLOP CIRCUITS; MICROPROCESSOR CHIPS; SIGNAL TO NOISE RATIO; SOFTWARE ENGINEERING;

TURBO CODES;

EID: 18644375283     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

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