A defect tolerant self-organizing nanoscale SIMD architecture

International Conference on Architectural Support for Programming Languages and Operating Systems - ASPLOS

Volumn , Issue , 2006, Pages 241-251

  Patwardhan, Jaidev P ^a   Johri, Vijeta ^a   Dwyer, Chris ^b   Lebeck, Alvin R ^a  

^a Duke University   (United States)

^b Duke University   (United States)

Author keywords

Bit serial; Data parallel; Defect tolerance; DNA; Nanocomputing; Self organizing; SIMD

Indexed keywords

DATA PARALLEL PROGRAMS; DEFECT TOLERANT ARCHITECTURES; NANOCOMPUTING; SWITCHING SPEEDS;

CMOS INTEGRATED CIRCUITS; DEFECT DENSITY; LITHOGRAPHY; PARALLEL PROGRAMMING; SELF ORGANIZING MAPS; SUPERVISORY AND EXECUTIVE PROGRAMS; SWITCHING;

COMPUTER ARCHITECTURE;

EID: 34547456541     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1168857.1168888     Document Type: Conference Paper

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