Towards defect-tolerant nanoscale architectures

2006 6th IEEE Conference on Nanotechnology, IEEE-NANO 2006

Volumn 1, Issue , 2006, Pages 331-334

  Moritz, Csaba Andras ^a   Wang, Teng ^a  

^a UNIVERSITY OF MASSACHUSETTS   (United States)

Author keywords

Defect tolerance; Processor; Semiconductor nanowire

Indexed keywords

CMOS INTEGRATED CIRCUITS; DEFECTS; INTEGRATED CIRCUIT LAYOUT; NANOWIRES; SELF ASSEMBLY; TWO DIMENSIONAL;

DEFECT TOLERANCE; NANOSCALE ARCHITECTURES; SEMICONDUCTOR NANOWIRES;

NANOELECTRONICS;

EID: 42549134505     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/nano.2006.247643     Document Type: Conference Paper

References (16)

1. Y. Cui and C. M. Lieber, "Functional nanoscale electronic devices assembled using silicon nanowire building blocks, Science, 2001.
2. A. DeHon, "Array-based architecture for FET-based, nanoscale electronics", IEEE Transactions on Nanotechnology, 92(1), 2003.
3. A. DeHon. "Nanowire-based programmable architectures", ACM Journal on Emerging Technologies in Computing Systems, 1(2), 2005.
4. A. DeHon and M. J. Wilson, "Sublithographic programmable logic arrays", Proceedings of the International Symposium on Field Programmable Gate Arrays, FPGA'04, 2004.
5. S. C. Goldstein and M. Budiu, "Nanofabrics: Spatial computing using molecular electronics", The 28th Annual International Symposium on Computer Architecture, ISCA'01, 2001.
6. A. B. Greytak, L. J. Lauhon, M. S. Gudiksen, and C. M. Lieber, "Growth and transport properties of complementary germanium nanowire field-effect transistors, Applied Physics Letters}, 84(21), May 2004.
7. Y. Huang, X. Duan, Y. Cui, L. Lauhon, K.-Y. Kim, and C. Lieber, Logic gates and computation from assembled nanowire building blocks, Science, 1313(294), 2001.
8. Y. Huang, X. Duan, Q. Wei, and C. Lieber, "Directed assembly of one-dimensional nanostructures into functional networks", Science, 2001.
9. K. K. Likharev, "CMOL: Devices, circuits, and architectures", Introducing Molecular Electronics, 2004.
10. R. E. Lyions and W. Vanderkulk, "The use of triple modular redundancy to improve computer reliability", IBM Journal of Research and Development, 6(2), 1962.
11. X. Ma, D. Strukov, J. H. Lee, and K. Likharev, "Afterlife for silicon: CMOL circuit architectures", 5th IEEE Conference on Nanotechnology, 2005.
12. C. A. Moritz, "Exploring NASICs and a comparison with CMOL: an architect's perspective", Third Advanced Research and Development Agency, workshop, 2006.
13. C. A. Moritz and T. Wang, "Latching on the wire and pipelining in nanoscale designs", Non-Silicon Computing Workshop, NSC-3, 2004.
14. T.Wang, M. Bennaser, Y. Guo, and C. A. Moritz, "Wire-streaming processors on 2-D nanowire fabrics", Nanotech 2005, Nano Science and Technology Institute, May 2005.
15. T. Wang, M. Bennaser, Y. Guo, and C. A. Moritz, "Self-healing wire-streaming processors on 2-d semiconductor nanowire fabrics", Nanotech 2006. Nano Science and Technology Institute, May 2006.
16. st ACM Conference on Computing Frontiers, pp 503-511, New York, USA, 2004