Does the brain really outperform rent's rule?

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn , Issue , 2008, Pages 640-643

  Beiu, Valeriu ^a,b,c   Ibrahim, Walid ^a,b  

^a UNITED ARAB EMIRATES UNIVERSITY   (United Arab Emirates)

^b Center for Neural Inspired Nano Architectures (CNINA)

^c UNIVERSITY OF ULSTER   (United Kingdom)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER NETWORKS; TECHNICAL PRESENTATIONS; TOPOLOGY;

INTERNATIONAL SYMPOSIUM; RENT'S RULE;

ELECTRIC NETWORK TOPOLOGY;

EID: 51749103333     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISCAS.2008.4541499     Document Type: Conference Paper

References (39)

1. International Technology Roadmap for Semiconductors, 2005 Edition, SEMATECH, Austin, TX, USA, http://public.itrs.net/
2. R.K. Cavin et al., "Research directions and challenges in nanoelectronics," J. Nanoparticle Res., vol. 8, Dec. 2006, pp. 841-858.
3. D.A.B. Miller, "Optical for low-energy communication inside digital processors: Quantum detectors, sources, and modulators as efficient impedance converters," Optics Lett., vol. 14, Jan. 15, 1989, pp. 146-148.
4. T. Sakurai, "Design challenges for 0.1μm and beyond," Proc. ASP-DAC'00, Tokyo, Japan, Jan. 2000, pp. 553-558.
5. J.A. Davis et al., "Interconnect limits on gigascale integration (GSI) in the 21st century," Proc. IEEE, vol. 89, Mar. 2001, pp. 305-324.
6. J.D. Meindl, "Beyond Moore's law: The interconnect era," Comp. Sci. & Eng., vol. 5, Jan. 2003, pp. 20-24.
7. Intel, http://www.intel.com/pressroom/archive/releases/20070 918corp_a.htm?iid=tech_arch_32nm+body_pressrelease
8. V. Beiu, and W. Ibrahim, "On computing nano-architectures using unreliable nano-devices," Chp. 12 in S.E. Lyshevski (Ed.): Handbook of Nano and Molecular Electronics, Taylor & Francis, London, UK, May 2007, pp. 12.1-49.
9. S.A. McKee (Ed.), Special Issue on Reliable Computing, ACM J. Emerg. Tech. Comp. Sys., vol. 3, Jul. 2007.
10. S.-L. Jeng et al., "A review of reliability research on nanotechnology," IEEE Trans. Reliab., vol. 56, Sep. 2007, pp. 401-410.
11. C. Lau et al. (Eds.), Special Issue on Nano-electronic Circuits & Nano-architectures, IEEE Trans. Circ. & Sys. I, vol. 54, Nov. 2007.
12. B.S. Landman, and R.L. Russo, "On a pin versus block relationship for partitions of logic graphs," IEEE Trans. Comp., vol. C-20, Dec. 1971, pp. 1469-1479.
13. E.F. Rent, "Microminiature packaging - Logic block to pin ratio," IBM Memoranda, Nov. 28 & Dec. 12, 1960 (see [15]).
14. M.Y. Lanzerotti et al., "Interpretation of Rent's rule for ultra-large-scale integrated circuit designs, with an application to wirelength distribution models," IEEE Trans. VLSI Sys., vol. 12, Dec. 2004, pp. 1330-1347.
15. M.Y. Lanzerotti et al., "Microminiature packaging and integrated circuitry: The work of E.F. Rent, with an application to on-chip interconnection," IBM J. R&D, vol. 49, Jul. 2005, pp. 777-803.
16. H.B. Bakoglu, Circuits, Interconnections, and Packaging for VLSI, Addison-Wesley, Reading, MA, USA, Jan. 1990.
17. M.Y. Lanzerotti et al., "Predicting interconnect requirements in ultra-large-scale integrated control logic circuitry," Proc. SLIP'05, San Francisco, CA, USA, Apr. 2005, pp. 43-50.
18. J.A. Davis et al., "A stochastic wire-length distribution for gigascale integration (GSI) - Part I," IEEE Trans. Electr. Dev., vol. 45, Mar.1998, pp. 580-589.
19. J.A. Davis et al., "A stochastic wire-length distribution for gigascale integration (GSI) - Part II," IEEE Trans. Electr. Dev., vol. 45, Mar. 1998, pp. 590-597.
20. W.E. Donath, "Placement and average interconnection lengths of computer logic," IEEE Trans. Circ. & Sys., vol. 26, Apr. 1979, pp. 272-277.
21. J. Dambre et al., "Toward the accurate prediction of placement wire length distributions in VLSI circuits," IEEE Trans. VLSI Sys., vol. 12, Apr. 2004, pp. 339-348.
22. P. Christie, and D. Stroobandt, "The interpretation and application of Rent's rule," IEEE Trans. VLSI Sys., vol. 8, Dec. 2000, pp. 639-648.
23. S. Das et al., "Calibration of Rent's rule models for three-dimensional integrated circuits," IEEE Trans. VLSI Sys., vol. 12, Apr. 2004, pp. 359-366.
24. A. Kumar, and S. Tiwari, "Testing and defect tolerance: A Rent's rule based analysis and implications on nanoelectronics," Proc. DFT'04, Ithaca, NY, USA, Oct. 2004, pp. 280-288.
25. J. Xu, Topological Structure and Analysis of Interconnection Networks, Springer, New York, NY, USA, Jan. 2002.
26. Q. Wen, and D.B. Chklovskii, "Segregation of the brain into gray and white matter: A design minimizing conduction delays," PLoS Comp. Biol., vol. 1, Dec. 2005, pp. 617-630.
27. S.B. Laughlin, and T.J. Sejnowski, "Communication in neural networks," Science, vol. 301, Sep. 2003. pp. 1870-1874.
28. K. Zhang, and T.J. Sejnowski, "A universal scaling law between gray matter and white matter of cerebral cortex," Proc. Natl. Acad. Sci., vol. 97, May 2000, pp. 5621-5626.
29. Y. Saad, and M.H. Schultz, "Topological properties of hypercubes," IEEE Trans. Comp., vol. 37, Jul. 1988, pp. 867-872.
30. L.N. Bhuyan, and D.P. Agrawal, "Generalized hypercube and hyperbus structures for a computer network," IEEE Trans. Comp., vol. 33, Apr. 1984, pp. 323-333.
31. L.D. Wittie, "Communication structures for large networks of microcomputers," IEEE Trans. Comp., vol. 30, Apr. 1981, pp. 264-273.
32. K. Ghose, and K.R. Desai, "Hierarchical cubic networks," IEEE Trans. Comp., vol. 6, Apr. 1995, pp. 427-435.
33. F.P. Preparata, and J. Vuillemin, "The cube-connected cycles: A versatile network for parallel computation," Comm. ACM, vol. 24, May 1981, pp. 300-309.
34. E. Ganesan, and D.K. Pradhan, "The hyper-deBruijn networks: Scalable versatile architecture," IEEE Trans. Par. & Distrib. Sys., vol. 4, Sep. 1993, pp. 962-978.
35. S. Ohring, and S.K. Das, "Folded Petersen cube networks: New competitors for the hypercubes," IEEE Trans. Par. & Distrib. Sys., vol. 7, Feb. 1996, pp. 151-168.
36. D. Hamerstrom, "The connectivity analysis of simple associations -or- How many connections do we need?," Proc. NIPS'87, Denver, CO, USA, 1988, pp. 338-347.
37. V. Beiu et al., "On global communications for nano-architectures - Brain vs. Rent's rule," Proc. DCIS'07, Seville, Spain, Nov. 2007, pp. 305-310.
38. D. Hammerstrom, "Biologically inspired nanoarchitectures," CANDE'07, Long Beach, CA, USA, Sep. 2007, http://web.cecs.pdx.edu/~strom/ danh_cande07.pdf
39. B.A.M. Madappuram et al., "On hybrid network topologies for future nano-architectures," VLSI-Symp'08, Honolulu, HI, USA, Jun. 2008.