Predicting interconnect requirements in ultra-large-scale integrated control logic circuitry

International Workshop on System Level Interconnect Prediction, SLIP

Volumn , Issue , 2005, Pages 43-50

  Lanzerotti, M Y ^a   Fiorenza, G ^a   Rand, R A ^a  

^a IBM T J WATSON RESEARCH CENTER   (United States)

Author keywords

Rent, interconnect; Routing; Wire length distribution model

Indexed keywords

RENT, INTERCONNECT; ROUTING; WIRE-LENGTH DISTRIBUTION MODELS;

DATA ACQUISITION; INTEGRATED INJECTION LOGIC CIRCUITS; MICROPROCESSOR CHIPS; PARAMETER ESTIMATION;

INTERCONNECTION NETWORKS;

EID: 30944440917     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1053355.1053366     Document Type: Conference Paper

References (24)

1. Bakoglu, H. B. Circuits, Interconnections, and Packaging for VLSI. New York: Addison-Wesley, 1990.
2. Landman, B. S. and Russo, R. L. On a Pin Versus Block Relationship for Partitions of Logic Graphs. IEEE Trans. Computers, C-20, (Dec. 1971), 1469-1479.
3. Stroobandt, D. Analytical methods for a priori wirelength estimates in computer systems. Ph.D. Dissertation, University of Ghent, Faculty of Applied Sciences, 1998.
4. Stroobandt, D. A Priori Wirelength Estimates for Digital Design. Boston: Kluwer Academic Publishers, 2001.
5. Verplaetse, P., Stroobandt, and Van Campenhout, J. A stochastic model for the interconnection topology of digital circuits. IEEE Trans. VLSI Systems, 9, (Dec. 2001), 938-942.
6. Verplaetse, P., Dambre, J., Stroobandt, D., and Van Campenhout, J. On partitioning vs. placement Rent properties. In Proceedings of the Int. Workshop on System-Level Interconnect Prediction. (Mar. 2001), ACM Press, NY.
7. Dambre, J., Verplaetse, P., Stroobandt, D., Van Campenhout, J. A comparison of various terminal-gate relationships for interconnect prediction in VLSI circuits. IEEE Trans. VLSI Systems, 11, (Feb. 2003), 24-34.
8. Dambre, J. Prediction of interconnect properties for digital circuit design and exploration, Ph.D. Dissertation, University of Ghent, Dept. of Electronics and Information Systems, 2003.
9. Dambre, J. Personal Communication, 2003.
10. Donath, W. E. Placement and average interconnection lengths of computer logic. IEEE Trans. Circuits and Systems, CAS-26, (April 1979), 272-277.
11. Donath, W. E. Wirelength distribution for placements of computer logic. IBM J. Res. Dev., 25, (May 1981), 152-155.
12. Davis, J. A., De, V. K., Meindl, J. D. A stochastic wire-length distribution for gigascale integration (GSI) - Pans I, II. IEEE Trans. Electron Devices, 45, (Mar. 1998), 580-597.
13. Davis, J. A. Ph.D. Thesis, Georgia Inst. Tech., 1999.
14. Christie, P., and Stroobandt, D. The interpretation and application of Rent's rule. IEEE Trans. VLSI Systems, 8, (Dec. 2000), 639-648.
15. Lanzerotti, M. Y., Fiorenza, G., and Rand, R. Assessment of on-chip wire-length distribution models. IEEE Trans. VLSI Systems, 12, (Oct. 2004), 1108-1112.
16. Warnock, J. D., Keaty, J., Petrovick, J., Clabes, J., Kircher, C. J., Krauter, B., Restle, P., Zoric, B., an Anderson, C. J. The circuit and physical design of the POWER4 microprocessor, IBM J. Res. Dev., 46, (Jan. 2002), 27-51.
17. Karypis, G., and Selvakkumaran, N. Personal Communication, Oct. 2003.
18. Karypis, G., and Kumar, V. (1998). hMetis: A Hypergraph Partitioning Package. [Online]. Available: http://www-users.cs.umn.edu/karypis/metis/hmetis/index.html.
19. Gent, I. P., Grant, S. A., MacIntyre, E., Prosser, P., Shaw, P., Smith, B. M., and Walsh, T. How Not To Do It. Research Report 97-27, Univ. of Leeds School of Comp, Stu., May 1997.
20. Caldwell, A. E., Kahng, A. B., Kennings, A. A., Markov, I. L. Hypergraph Partitioning for VLSI CAD: Methodology for Heuristic Development, Experimentation and Reporting. In Proceedings of the Design Automation Conf., 1999.
21. Yang, X., Bozogzadeh, E., Sarrafzadeh, M. Wirelength estimation based on Rent exponents of partitioning and placement. In Proceedings of the Int. Workshop on System-Level Interconnect Prediction, (Mar. 2001). ACM Press, NY.
22. Christie, P. A differential equation for placement analysis. IEEE Trans. VLSI Systems, 9, (Dec. 2001), 913-921.
23. Dambre, J., Verplaetse, P., Stroobandt, D., and Van Campenhout, J. On Rent's rule for rectangular regions. In Proceedings of the Int. Workshop on System-Level Interconnect Prediction, (Mar. 2001). ACM Press, NY, 2001, 49-56.
24. Stroobandt, D. A priori wirelength distribution models for multiterminal nets. IEEE Trans. VLSI Systems, 11, (Feb. 2003), 35-43.