-
1
-
-
4244057196
-
-
ITRS, 2007 Edition, pp
-
ITRS, Process Integration, Devices, and Structures, 2007 Edition, pp. 35-37.
-
Process Integration, Devices, and Structures
, pp. 35-37
-
-
-
2
-
-
33847707730
-
Technology for sub-50 nm DRAM and NAND flash manufacturing
-
K. Kim, "Technology for sub-50 nm DRAM and NAND flash manufacturing," IEDM, 2005, pp. 333-336.
-
(2005)
IEDM
, pp. 333-336
-
-
Kim, K.1
-
3
-
-
46049088349
-
2 Cell Size using TANOS (Si -Oxide - A1203 - TaN) Cell Technology
-
2 Cell Size using TANOS (Si -Oxide - A1203 - TaN) Cell Technology, IEDM, 2006, pp. 54-55.
-
(2006)
IEDM
, pp. 54-55
-
-
Park, Y.1
-
4
-
-
28744456880
-
High-k materials for nonvolatile memory applications
-
J. Van Houdt, "High-k materials for nonvolatile memory applications", IRPS, 2005, pp. 234-239.
-
(2005)
IRPS
, pp. 234-239
-
-
Van Houdt, J.1
-
5
-
-
34548729187
-
Reliability And Processing Effects Of Bandgap Engineered SONOS (BE-SONOS) Flash Memory
-
S. Y. Wang et al, "Reliability And Processing Effects Of Bandgap Engineered SONOS (BE-SONOS) Flash Memory", IRPS, 2007, pp. 171-176.
-
(2007)
IRPS
, pp. 171-176
-
-
Wang, S.Y.1
-
6
-
-
18844429264
-
SONOS Device With Tapered Bandgap Nitride Layer
-
K. H. Wu et al, "SONOS Device With Tapered Bandgap Nitride Layer", IEEE Tran. on Electron Dev. v.52 no.5, 2005, pp.987-992.
-
(2005)
IEEE Tran. on Electron Dev
, vol.52
, Issue.5
, pp. 987-992
-
-
Wu, K.H.1
-
7
-
-
19944378108
-
Two-bit SONOS type Flash using a band engineering in the nitride layer
-
H.C.Chien et al., "Two-bit SONOS type Flash using a band engineering in the nitride layer", Microelectron. Eng., v.80, 2005, pp. 256.
-
(2005)
Microelectron. Eng
, vol.80
, pp. 256
-
-
Chien, H.C.1
-
8
-
-
47249154755
-
Band Engineered Charge Trap Layer for highly Reliable MLC Flash Memory
-
Z. Huo et al., "Band Engineered Charge Trap Layer for highly Reliable MLC Flash Memory", VLSI Tech. Symp., 2007, pp. 138-139.
-
(2007)
VLSI Tech. Symp
, pp. 138-139
-
-
Huo, Z.1
-
9
-
-
0028448736
-
Silicon oxynitride as a tunable optical material
-
S.C Bayliss, "Silicon oxynitride as a tunable optical material" Journal of Physics Condensed Matter, v.6, 1994, pp. 4961-70.
-
(1994)
Journal of Physics Condensed Matter
, vol.6
, pp. 4961-4970
-
-
Bayliss, S.C.1
-
10
-
-
0000662431
-
Preparation of Thin Dielectric Film for Nonvolatile Memory by Thermal Oxidation of Si-Rich LPCVD Nitride
-
H. Wong et al, "Preparation of Thin Dielectric Film for Nonvolatile Memory by Thermal Oxidation of Si-Rich LPCVD Nitride", Journal of Electrochemical Society, v. 148, 2005, pp.G275-G278.
-
(2005)
Journal of Electrochemical Society
, vol.148
-
-
Wong, H.1
-
11
-
-
33747094470
-
Electron trap density distribution of Si-rich silicon nitride extracted using the modified negative charge decay model of silicon-oxide-nitride-oxide-silicon structure at elevated temperatures
-
K. Tae Hun et al., "Electron trap density distribution of Si-rich silicon nitride extracted using the modified negative charge decay model of silicon-oxide-nitride-oxide-silicon structure at elevated temperatures", App. Phys. Lett., v. 89, 2006, pp. 63508(1-3).
-
(2006)
App. Phys. Lett
, vol.89
, Issue.1-3
, pp. 63508
-
-
Tae Hun, K.1
-
12
-
-
0037407807
-
Characterization of SONOS Oxynitride nonvolatile semiconductor memory devices
-
S. J. Wrazien et al, "Characterization of SONOS Oxynitride nonvolatile semiconductor memory devices", Solid-State Electronics, v. 47, Issue 5, 2003, pp. 885-891.
-
(2003)
Solid-State Electronics
, vol.47
, Issue.5
, pp. 885-891
-
-
Wrazien, S.J.1
-
13
-
-
33748465169
-
Density functional theory study of deep traps in silicon nitride memories
-
1-3
-
M. Petersen, "Density functional theory study of deep traps in silicon nitride memories" App. Phys. Lett., v.89, 2006, pp. 053511 (1-3).
-
(2006)
App. Phys. Lett
, vol.89
, pp. 053511
-
-
Petersen, M.1
-
14
-
-
46149123005
-
Comprehensive Simulation of Program, Erase and Retention in Charge Trapping Flash Memories
-
A. Paul et al., "Comprehensive Simulation of Program, Erase and Retention in Charge Trapping Flash Memories", IEDM, 2006, pp. 1-4.
-
(2006)
IEDM
, pp. 1-4
-
-
Paul, A.1
-
15
-
-
34250753325
-
Characterization of Charge Traps in MetalOxide-Nitride-Oxide-Semiconductor (MONOS) Structures for Embedded Flash Memories
-
T. Ishida et al., "Characterization of Charge Traps in MetalOxide-Nitride-Oxide-Semiconductor (MONOS) Structures for Embedded Flash Memories", IRPS, 2006, pp. 516-522.
-
(2006)
IRPS
, pp. 516-522
-
-
Ishida, T.1
-
16
-
-
34548801917
-
Improving The Endurance Characteristics Through Boron Implant At Active Edge In 1 G NAND Flash
-
D. Kang et al., "Improving The Endurance Characteristics Through Boron Implant At Active Edge In 1 G NAND Flash", IRPS, 2007, pp. 652-653.
-
(2007)
IRPS
, pp. 652-653
-
-
Kang, D.1
-
17
-
-
33751026939
-
Charge Trapping Memory Cell of TANOS (Si-Oxide-SiN-A1203-TaN) Structure Compatible to Conventional NAND Flash Memory
-
C. H. Lee, "Charge Trapping Memory Cell of TANOS (Si-Oxide-SiN-A1203-TaN) Structure Compatible to Conventional NAND Flash Memory", NVSMW, 2006, pp. 54-55.
-
(2006)
NVSMW
, pp. 54-55
-
-
Lee, C.H.1
-
18
-
-
0025522099
-
Chemical Composition, Charge Trapping, and Memory Properties of Oxynitride Films for MNOS Devices
-
V. J. Kapoor et. al, "Chemical Composition, Charge Trapping, and Memory Properties of Oxynitride Films for MNOS Devices", J. Electrochem. Soc, v. 137, 1990, pp. 3589-3596.
-
(1990)
J. Electrochem. Soc
, vol.137
, pp. 3589-3596
-
-
Kapoor, V.J.1
et., al.2
-
19
-
-
38349035934
-
Spatial Distribution of Charge Traps in a SONOS-Type Flash Memory Using a High-A: Trapping Layer
-
G. Zhang, "Spatial Distribution of Charge Traps in a SONOS-Type Flash Memory Using a High-A: Trapping Layer", IEEE Tran. on Electron Dev., v.54, no. 12, 2007, pp. 3317-3324.
-
(2007)
IEEE Tran. on Electron Dev
, vol.54
, Issue.12
, pp. 3317-3324
-
-
Zhang, G.1
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