Reliability and processing effects of bandgap engineered sonos (BE-SONOS) flash memory

Annual Proceedings - Reliability Physics (Symposium)

Volumn , Issue , 2007, Pages 171-176

  Wang, Szu Yu ^a,b   Lue, Hang Ting ^a   Lai, Erh Kun ^a,b   Yang, Ling Wu ^a   Yang, Tahone ^a   Chen, Kuang Chao ^a   Gong, Jeng ^b   Hsieh, Kuang Yeu ^a   Liu, Rich ^a   Lu, Chih Yuan ^a  

^a MACRONIX INTERNATIONAL CO LTD   (Taiwan)

^b NATIONAL TSING HUA UNIVERSITY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

CHARGE TRAPPING; ELECTRON TUNNELING; ENERGY GAP; LOGIC CIRCUITS; RELIABILITY ANALYSIS;

DATA RETENTION; TRAPPING LAYERS; TUNNELING BARRIERS;

FLASH MEMORY;

EID: 34548729187     PISSN: 00999512     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/RELPHY.2007.369888     Document Type: Conference Paper

References (12)

1. H.T. Lue, S.Y. Wang, E.K. Lai, Y.H. Shih, S.C. Lai, L.W. Yang, K.C. Chen, J. Ku, K.Y. Hsieh, R. Liu, and C.Y. Lu, "BE-SONOS: A Bandgap Engineered SONOS with Excellent Performance and Reliability", Tech. Digest 2005 International Electron Devices Meeting, pp. 547-550, 2005.
2. K. Kim, "Technology for sub 50 nm node DRAM and NAND Flash Manufacturing", Tech. Digest 2005 International Electron Devices Meeting, pp. 539-543, 2005.
3. +-poly gate nitride-trapping non-volatile memory device with excellent endurance and retention properties", Proceedings of the International Reliability Physics Symposium (IRPS), session 2D-3, pp. 168-174, 2005.
4. H.T. Lue, S.Y. Wang, Y. H. Hsiao, E.K. Lai, L.W. Yang, T. Yang, K.C. Chen, K. Y. Hsieh, R. Liu, and C.Y. Lu, "Reliability Model of Bandgap Engineered SONOS (BE-SONOS)", in IEDM Tech. Dig., 2006, session 18-5.
5. H. T. Lue, S. Y. Wang, E. K. Lai, M. T. Wu, L. W. Yang, K. C. Chen, J. Ku, K. Y. Hsieh, R. Liu, and C. Y. Lu, "A Novel P-Channel NAND-Type Flash Memory with 2-Bit/Cell Operation and High Programming Throughput (>20 MB/sec)," in IEDM Tech. Dig., 2005, session 13-7, pp. 331-334.
6. E.K. Lai, H.T. Lue, Y.H. Hsiao, J.Y. Hsieh, S.C. Lee, C.P. Lu, S.Y. Wang, L.W. Yang, K.C. Chen, J. Gong, K.Y. Hsieh, J.Ku, R. Liu, and C.Y. Lu, "A Highly Stackable Thin-Film Transistor (TFT) NAND-Type Flash Memory", VLSI Technology Symposium, pp. 56-57, 2006.
7. E.K. Lai, H.T. Lue, Y.H. Hsiao, J.Y. Hsieh, S.C. Lee, C.P. Lu, S.Y. Wang, L.W. Yang, K.C. Chen, J. Gong, K.Y. Hsieh, J.Ku, R. Liu, and C.Y. Lu, "A Multi-Layer Stackable Thin-Film Transistor (TFT) NAND-Type Flash Memory", in IEDM Tech. Dig., 2006, session 2-4.
8. IRPS High-k gate dielectric short course, 2006.
9. H. T. Lue, P. Y. Du, S. Y. Wang, E. K. Lai, K. Y. Hsieh, R. Liu, and C. Y. Lu, "A novel gate-sensing and channel sensing transient analysis method for real-time monitoring of charge vertical location in SONOS-type devices and its applications in reliability studies", International Reliability Physics Symposium (IRPS) 2007, 3A-4 (this conference).
10. K. K. Likharev, "Layered tunnel barriers for non-volatile memory", Applied Physic Letters, pp. 2137-2139, 1998.
11. H.T. Lue, Y.H. Shih, K.Y. Hsieh, R. Liu, and C.Y. Lu, "A transient analysis method to characterize the trap vertical location in nitride-trapping devices", IEEE Electron Device Letters, vol. 25, pp.816-818, 2004.
12. S. Y. Wang, H. T. Lue, E. K. Lai, L. W. Yang, J. Gong, K. C. Chen, K. Y. Hsieh, J. Ku, and C. Y. Lu, "Effect of fabrication process on the charge trapping behavior of SiON thin films", Solid-State Electronics, vol. 50, pp. 1171-1174, 2006