Degradation effects in a-si:h thin film transistors and their impact on circuit performance

IEEE International Reliability Physics Symposium Proceedings

Volumn , Issue , 2008, Pages 158-167

  Allee, David R ^a   Clark, Lawrence T ^a   Shringarpure, Rahul ^a   Venugopal, Sameer M ^a   Li, Zi P ^a   Bawolek, Edward J ^a  

^a ARIZONA STATE UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DEGRADATION EFFECTS; GATE VOLTAGES; RELIABILITY PHYSICS;

AMORPHOUS MATERIALS; FIELD EFFECT TRANSISTORS; MOSFET DEVICES; RELIABILITY; SEMICONDUCTING SILICON COMPOUNDS; SILICON; THICK FILMS; THIN FILM DEVICES; THIN FILM TRANSISTORS; THIN FILMS; TRANSISTORS;

AMORPHOUS SILICON;

EID: 51549089634     PISSN: 15417026     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/RELPHY.2008.4558878     Document Type: Conference Paper

References (34)

1. K. Long, A.Z. Kattamis, I.C. Cheng, H. Gleskova, S. Wagner, and J.C. Sturm, "Stability of amorphous-silicon TFTs deposited on clear plastic substrates at 250C to 280C," IEEE Electron Device Letters, vol. 27, no. 2, February 2006, pp. 111-113.
2. th Annual Flexible Display Conference, Phoenix, AZ, Feb 6-9, 2006.
3. C. Wu, S. Theiuss, G. Gu, M. Lu, J. Sturm, S. Wagner, and S. Forrest, "Integration of organic LEDs and amorphous Si TFTs onto flexible and lightweight metal foil substrates," IEEE Electron Device Letters, 18, Dec. 1997, pp. 609 - 612.
4. Nathan, A. Kumar, K. Sakariya, P. Servati, S. Sambandan, and D. Striakhilev, "Amorphous silicon thin film transistor integration for Organic LED displays on glass and plastic," IEEE Journal of Solid-State Circuits, 29, Sept 2004, pp. 1477-1486.
5. G.B. Raupp, S.M. O'Rourke, C. Moyer, B.P. O'Brien, S.K. Ageno, D.E. Loy, E.J. Bawolek, D.R. Allee, S.M. Venugopal, J. Kaminski, D. Bottesch, J. Dailey, K. Long, M. Marrs, N.R. Munizza, H. Haverinen, N. Colaneri," Low-temperature amorphous-silicon backplane technology development for flexible displays in a manufacturing pilot-line environment," Journal for the Society of Information Displays, Vol. 15, No. 7, 2007, pp. 445-454.
6. H. Lebrun, T. Kretz, J. Magarino and N. Szydlo, "Design of integrated drivers with amorphous TFTs for Small Displays, " Digest Society for Information Displays, 2005, pp. 950-953.
7. R. Stewart, and H. Lebrun, "Reliability and lifetime of SASID Displays," presented at the International Displays Workshop, Nagoya, Japan, Nov 1997.
8. Sameer M. Venugopal, and David R Allee, "Integrated a-Si:H source drivers for 4" QVGA electrophoretic display on flexible stainless steel substrate," IEEE Journal of Display Technology, Vol. 3, No. 1, March 2007, pp. 57-63.
9. Y. Kaneko, A. Sasano, and T. Tsukada, "Characterization of instability in amorphous silicon thin-film transistors," Journal of Applied Physics, vol. 69, no. 10, 15 May 1991, pp. 7301-7305
10. F.R. Libsch, and J. Kanicki, "Bias-stress-induced stretched-exponential time dependence of charge injection and trapping in amorphous thin-film transistors," Applied Physics Letters, vol. 62, no. 11, 15 March 1993, pp. 1286-1288.
11. H.C. Slade, and M.S. Shur, "Analysis of bias stress on unpassivated hydrogenated amorphous silicon thin-film transistors," IEEE Transactions on Electron Devices, vol. 45, no. 7, July 1998, pp. 1548-1553.
12. C. Chiang, J. Kanicki, and K. Takechi, "Electrical instability of hydrogenated amorphous silicon thin-film transistors for active matrix liquid crystal displays," Japanese Journal of Applied Physics, vol. 37, 1998, pp. 4704-4710
13. H. Gleskova, and S. Wagner, "DC-gate-bias stressing of a-Si :H TFTs fabricated at 150C on polyimide foil," IEEE Transactions on Electron Devices, 48, Aug 2001, pp. 1667-1671.
14. Rahul Shringarpure, Sameer Venugopal, Zi Li, Lawrence T. Clark, David R. Allee, Edward Bawolek, and Daniel Toy, "Circuit Simulation of Threshold Voltage Degradation in a-Si:H TFT's Fabricated at 175°C," IEEE Transactions on Electron Devices, Vol. 54, No. 7, July 2007, pp. 1781-1783.
15. K. Karim, A. Nathan, M. Hack, and W. Milne, "Drain bias dependence of threshold voltage stability of amorphous silicon TFTs," IEEE Electron Device Letters, 25, Apr 2004, pp. 188-190.
16. th International Conference on Solid-State and Integrated Circuit Technology, Oct 1998, pp. 834-837.
17. R. Oritsuki, T. Horii, A. Sasano, K. Tsutsui, T. Koizumi, Y. Kaneko, and T. Tsukada, " Threshold voltage shift of amorphous silicon thin-film transistors during pulse operation," Japanese Journal of Applied Physics, vol. 30, Dec 1991, pp. 3719-3723.
18. Sameer M. Venugopal, David R. Allee, Zi Li, and Lawrence T. Clark, "Threshold-voltage recovery of a-Si:H digital circuits," Journal of the Society for Information Displays, Vol. 14, No. 11, November 2006, pp. 1053-1057.
19. N. Ibaraki, M. Kigoshi, K. Fukuda, and J. Kobayashi, "Threshold voltage instability of a-Si:H TFT's in liquid crystal displays," J. Non-Crystalline Solids, vol. 115, 1989, pp. 138-140.
20. H. Aoki, "Dynamic characterization of a-Si TFT-LCD pixels", IEEE Trans. Electron Devices, vol. 43, Jan. 1996, pp. 31-39.
21. M. J. Powell, "The physics of amorphous-silicon thin-film transistors," IEEE Trans. Electron Devices, vol. 36, 1989, pp. 2753-2763.
22. M. Powell, "Charge trapping instabilities in amorphous silicon-silicon nitride thin film transistors," Applied Physics Letters, 43, 1983, pp.597-599.
23. M. Powell, C. van Berkel, A. Franklin, S. Deane and W. Milne, "Defect pool in amorphous-silicon thin-film transistors" Physical Review B, 45, 1992, pp. 4160.
24. A. Hepburn, J. Marshall, and C. Martin, "Metastable defects in amorphous silicon thin film transistors," Physical Review Letters, 56, 1986, pp. 2215-2218.
25. S.C. Deane and M.J. Powell, "Field-effect conductance in amorphous silicon thin-film transistors with a defect pool density of states," J. Appl. Phys., vol. 74(11), Dec. 1993, pp. 6655-6666.
26. P. Roblin, A. Samman, and S. Bibyk, "Simulation of Hot-electron trapping and aging of nMOSFETs", IEEE Trans. Electron Devices, Vol. 35, Dec. 1998, pp. 2229-2237.
27. Y. Leblebici, "Design considerations for CMOS digital circuits with improved hot-carrier reliability," Journal of Solid State Circuits, vol. 31, no. 7, July 1996, pp. 1014-1024.
28. Y. Tsividis, "Operation and Modeling of the MOS transistor", Second Edition, June 2003, pp. 154-156.
29. R. Shringarpure, et al, "Localization of gate biased induced threshold voltage degradation in a-Si:H TFT's", IEEE Electronic Device Letters, vol 29, no. 1, Jan 2008, pp. 93-95.
30. Jan Lohstroh, Evert Seevinck and Jan De Groot, "Worst-Case Static Noise Margin Criteria for Logic Circuits and Their Mathematical Equivalence," IEEE Journal of Solid-State Circuits, vol. sc-18, no. 6, December 1983, pp. 803-807.
31. Zi Li, Sameer Venugopal, Rahul Shringarpure, David R. Allee and Lawrence T. Clark, "Noise Margin Analysis of a-Si:H Digital Circuits," Journal for the Society of Information Displays, Vol. 15, No. 4, 2007, pp. 251-259
32. M.S. Shur, M.D. Jacunski, H.C. Slade and M. Hack, "Analytical Models for Amorphous and Poly silicon Thim Film Transistors," Journal of Information Display, vol. 3, 1995, pp. 223-235.
33. D.K. Schroder, and J.A. Babcock, "Negative bias temperature instability: Road to cross in deep submicron silicon semiconductor manufacturing," Journal of Applied Physics, vol. 94, no. 1, 1 July 2003, pp. 1-18.
34. K.S. Girota, Y.M. Choi, B.J. Kim, Y.R. Song, B. Choi, S.H. Yang, S. Kim, and S. Lim, "PECVD-based nanocrystalline-silicon TFT backplanes for large-sized AMOLED displays," Journal for the Society of Information Displays, Vol. 15, No. 2, 2007, pp. 113-118.