Noise-margin analysis of a-Si:H digital circuits

Journal of the Society for Information Display

Volumn 15, Issue 4, 2007, Pages 251-259

  Li, Zi ^a   Venugopal, Sameer ^a   Shringarpure, Rahul ^a   Allee, David R ^a   Clark, Lawrence T ^a  

^a ARIZONA STATE UNIVERSITY   (United States)

Author keywords

Amorphous silicon thin film transistors; Circuit aging; Noise margin; Threshold voltage shift

Indexed keywords

AMORPHOUS; AMORPHOUS-SILICON THIN-FILM TRANSISTORS; ANALYTICAL MODELS; CIRCUIT AGING; CIRCUIT DESIGNS; CIRCUIT NOISES; CONTINUOUS; DUTY-CYCLE; ELECTRICAL STRESSES; EVALUATING; EXPERIMENTAL MEASUREMENTS; LIFE-TIMES; MARGIN ANALYSES; METRICS; NOISE MARGIN; NOISE MARGINS; STATIC AND DYNAMICS; THRESHOLD-VOLTAGE SHIFT;

AMORPHOUS SILICON; DIGITAL ARITHMETIC; DIGITAL CIRCUITS; DIGITAL INTEGRATED CIRCUITS; INTEGRATED CIRCUIT MANUFACTURE; NETWORKS (CIRCUITS); SILICON; THIN FILM TRANSISTORS; THRESHOLD VOLTAGE; TRANSISTORS;

ELECTRIC NETWORK ANALYSIS;

EID: 51549105152     PISSN: 10710922     EISSN: None     Source Type: Journal    
DOI: 10.1889/1.2723882     Document Type: Article

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