Localization of gate bias induced threshold voltage degradation in a-Si:H TFTs

IEEE Electron Device Letters

Volumn 29, Issue 1, 2008, Pages 93-95

  Shringarpure, Rahul ^a   Venugopal, Sameer ^b   Clark, Lawrence T ^a   Allee, David R ^a   Bawolek, Edward ^b  

^a Arizona State University   (United States)

^b ARIZONA STATE UNIVERSITY   (United States)

Author keywords

Amorphous silicon thin film transistors (a Si:H TFTs); Circuit simulation; Display technology; Spice; Threshold voltage degradation

Indexed keywords

AMORPHOUS SILICON; CIRCUIT SIMULATION; DRAIN CURRENT; GATES (TRANSISTOR); SEMICONDUCTING SILICON; SPICE; THRESHOLD VOLTAGE;

AMORPHOUS SILICON THIN FILM TRANSISTORS; GATE BIAS; THRESHOLD VOLTAGE DEGRADATION;

THIN FILM TRANSISTORS;

EID: 37549007863     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/LED.2007.911609     Document Type: Article

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