Circuit simulation of threshold-voltage degradation in a-Si:H TFTs fabricated at 175 °C

IEEE Transactions on Electron Devices

Volumn 54, Issue 7, 2007, Pages 1781-1783

  Shringarpure, Rahul ^a   Venugopal, Sameer ^b   Li, Zi ^b   Clark, Lawrence T ^a   Allee, David R ^a   Bawolek, Edward ^b   Toy, Daniel ^b  

^a Arizona State University   (United States)

^b ARIZONA STATE UNIVERSITY   (United States)

Author keywords

Circuit simulation; Display technology; Hydrogenated amorphous silicon thin film transistor (a Si:H TFT); SPICE; Threshold voltage degradation

Indexed keywords

HYDROGENATED AMORPHOUS SILICON THIN-FILM TRANSISTOR; THRESHOLD-VOLTAGE DEGRADATION;

AMORPHOUS SILICON; CIRCUIT SIMULATION; FLIP FLOP CIRCUITS; MATHEMATICAL MODELS; SPICE; THRESHOLD VOLTAGE;

THIN FILM TRANSISTORS;

EID: 34447323594     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2007.899667     Document Type: Article

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