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Volumn , Issue , 2007, Pages 186-189

Advances in Multi-Gate MOSFET circuit design

Author keywords

[No Author keywords available]

Indexed keywords

MOSFET DEVICES; STATIC RANDOM ACCESS STORAGE;

EID: 50649121614     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICECS.2007.4510961     Document Type: Conference Paper
Times cited : (8)

References (17)
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  • 2
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    • Device and circuit-level analog performance trade-offs: A comparative study of planar bulk FETs versus FinFETs
    • V. Subramanian et al., "Device and circuit-level analog performance trade-offs: a comparative study of planar bulk FETs versus FinFETs," IEDM Techn. Dig., 2005.
    • (2005) IEDM Techn. Dig
    • Subramanian, V.1
  • 3
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    • Design and evaluation of basic analog circuits in an emerging MuGFET technology
    • G. Knoblinger et al., "Design and evaluation of basic analog circuits in an emerging MuGFET technology," Intern. SOI Conference Proc., 2005, pp. 39-40.
    • (2005) Intern. SOI Conference Proc , pp. 39-40
    • Knoblinger, G.1
  • 4
    • 39549102528 scopus 로고    scopus 로고
    • Circuit design issues in multi-gate FET CMOS technologies
    • C. Pacha et al., "Circuit design issues in multi-gate FET CMOS technologies," ISSCC Dig. of Techn. Papers, 2006, pp. 1656-1665.
    • (2006) ISSCC Dig. of Techn. Papers , pp. 1656-1665
    • Pacha, C.1
  • 5
    • 39549096358 scopus 로고    scopus 로고
    • A Low-Power Multi-Gate FET CMOS Technology with 13.9ps Inverter Delay, Large-Scale Integrated High Performance Digital Circuits and SRAM
    • K. von Arnim et al., "A Low-Power Multi-Gate FET CMOS Technology with 13.9ps Inverter Delay, Large-Scale Integrated High Performance Digital Circuits and SRAM," VLSI Techn. Symp., 2007.
    • (2007) VLSI Techn. Symp
    • von Arnim, K.1
  • 6
    • 0034258881 scopus 로고    scopus 로고
    • Analytic description of short-channel effects in fully-depleted double-gate and cylindrical, surrounding-gate MOSFETs
    • S.-H. Oh et al., "Analytic description of short-channel effects in fully-depleted double-gate and cylindrical, surrounding-gate MOSFETs," IEEE Electr. Dev. Let., vol. 21, no. 9, pp. 445-447, 2000.
    • (2000) IEEE Electr. Dev. Let , vol.21 , Issue.9 , pp. 445-447
    • Oh, S.-H.1
  • 7
    • 44849114018 scopus 로고    scopus 로고
    • Efficiency of Low-Power Design Techniques in Multi-Gate FET CMOS Circuits
    • C. Pacha et al., "Efficiency of Low-Power Design Techniques in Multi-Gate FET CMOS Circuits," Proc. of ESSCIRC, 2007, pp. 111-114.
    • (2007) Proc. of ESSCIRC , pp. 111-114
    • Pacha, C.1
  • 8
    • 44849084964 scopus 로고    scopus 로고
    • Layout Options for Stability Tuning of SRAM Cells in Multi-Gate-FET Technologies
    • F. Bauer et al., "Layout Options for Stability Tuning of SRAM Cells in Multi-Gate-FET Technologies," Proc. of ESSCIRC, 2007, pp. 392-395.
    • (2007) Proc. of ESSCIRC , pp. 392-395
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  • 9
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    • Analog Design Challenges and Trade-Offs using Emerging Materials and Devices
    • M. Fulde et al., "Analog Design Challenges and Trade-Offs using Emerging Materials and Devices," Proc. of ESSCIRC, 2007, pp. 123-126.
    • (2007) Proc. of ESSCIRC , pp. 123-126
    • Fulde, M.1
  • 10
    • 20444441991 scopus 로고    scopus 로고
    • Review on high-k dielectrics reliability issues
    • G. Ribes, et al., "Review on high-k dielectrics reliability issues," IEEE Trans. Device Mat. Rel., vol. 5, no. 1, pp. 5-19, 2005
    • (2005) IEEE Trans. Device Mat. Rel , vol.5 , Issue.1 , pp. 5-19
    • Ribes, G.1
  • 11
    • 50649084183 scopus 로고    scopus 로고
    • Transient Variations in Emerging SOI Technologies: Modeling and Impact on Analog/Mixed-Signal Circuits
    • M. Fulde et al., "Transient Variations in Emerging SOI Technologies: Modeling and Impact on Analog/Mixed-Signal Circuits," Proc. of ISCAS, 2006.
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  • 13
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    • Characterization of mixed-signal properties of MOSFETs with high-k (SiON/HfSiON/TaN) gate stacks
    • Z. Rittersma et al., "Characterization of mixed-signal properties of MOSFETs with high-k (SiON/HfSiON/TaN) gate stacks," IEEE Electr. Dev. Let., vol. 53, no. 5, pp. 1216-1225, 2006.
    • (2006) IEEE Electr. Dev. Let , vol.53 , Issue.5 , pp. 1216-1225
    • Rittersma, Z.1
  • 15
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    • Unique ESD Failure Mechanism in a MuGFET Technology
    • H. Gossner et al., "Unique ESD Failure Mechanism in a MuGFET Technology," IEDM Techn. Dig., 2006, pp. 1-4.
    • (2006) IEDM Techn. Dig , pp. 1-4
    • Gossner, H.1
  • 16
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    • C. C. Russ et al., "ESD Evaluation of the Emerging MuGFET Technology," EOS/ESD Symp., pp. 280-289, 2005.
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  • 17
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.