High-throughput hardware-efficient digit-serial architecture for field multiplication over GF(2m)

2007 6th International Conference on Information, Communications and Signal Processing, ICICS

Volumn , Issue , 2007, Pages

  Meher, P K ^a  

^a NANYANG TECHNOLOGICAL UNIVERSITY   (Singapore)

Author keywords

[No Author keywords available]

Indexed keywords

DIGIT-SERIAL ARCHITECTURE; INTERNATIONAL CONFERENCES;

SIGNAL PROCESSING;

EID: 50449084380     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICICS.2007.4449560     Document Type: Conference Paper

References (20)

1. [Online]. Available: http://www.csrc.nist.gov/publications
2. I. Blake, G. Seroussi, and N. P. Smart, Elliptic Curves in Cryptography. London Mathematical Society Lecture Note Series: Cambridge University Press, 1999.
3. S. K. Jain, L. Song, and K. K. Parhi, "Efficient semisystolic architectures for finite-field arithmetic," IEEE Trans. Very Large Scale Integration (VLSI) Systems, vol. 6, no. 1, pp. 101-113, Mar. 1998.
4. H. Wu, "Bit-parallel finite field multiplier and squarer using polynomial basis," IEEE Trans. Computers, vol. 51, no. 7, pp. 750-758, July 2002.
5. m)," IEEE Trans. Computers, vol. 53, no. 8, pp. 945-959, Aug. 2004.
6. J. L. Imaña, J. M. Sánchez, and F. Tirado, "Bit-parallel finite field multipliers for irreducible trinomials," IEEE Trans Computers, vol. 55, no. 5, pp. 520-533, May 2006.
7. Huapeng Wu, "Low complexity bit-parallel multiplier for a class of finite fields," in Proc. 2006 International Conference on Communications, Circuits and Systems, vol. 4, June 2006, pp. 565-568.
8. T. Beth and D. Gollmann, "Algorithm engineering for public key algorithm," IEEE Journal on Selected Areas in Communications, vol. 7, no. 4, 1989.
9. m)," in 2005 International Conference on Reconfigurable Computing and FPGAs (ReConFig 2005), Sept. 2005, p. 5.
10. m)," IEEE Trans. Very Large Scale Integration (VLSI) Systems, vol. 6, no. 1, pp. 101-113, Mar. 1998.
11. n) for elliptic curve cryptosystems," in 12th IEEE Mediterranean Electrotechnical Conference (IEEE MELECON), vol. 2, May 2004, pp. 779-782.
12. m)," in Proc. 18th IEEE Int. Conf. on Application-specific Systems, Architectures and Processors, ASAP 07, Montreal, July 2007, pp. 134-139.
13. m)," IEE Proceedings- Computers and Digital Techniques, vol. 145, no. 2, pp. 143-148, Mar. 1998.
14. m)," in Proc. 14th Annual IEEE International ASIC/SOC Conference, Sept. 2001, pp. 361-365.
15. m)," IEEE Trans. Very Large Scale Integration (VLSI) Systems, vol. 13, no. 4, pp. 476-483, Apr. 2005.
16. m)," in Proc. 2005 Asia and South Pacific Design Automation Conference (ASP-DAC-2005), vol. 2, Jan. 2005, pp. 1268-1271.
17. L. Song and K. K. Parhi, "Low-energy digit-serial/parallel finite field multipliers," Journal of VLSI Digital Processing, vol. 19, pp. 149-166, 1998.
18. 233)," in The 3rd International IEEE-NEWCAS Conference, June 2005, pp. 399-402.
19. National Institute of Standards and Technology, "FIPS 186-2, Digital Signature Standard (DSS), Federal Information Processing Standards Publication 186-2," 2000.
20. "Synposys, DesignWare. Foundry Libraries Mountain View, CA." [Online]. Available: http://www.synopsys.com/