An efficient digit-serial systolic multiplier for finite fields GF(2m)

Proceedings of the Annual IEEE International ASIC Conference and Exhibit

Volumn , Issue , 2001, Pages 361-365

  Kim, C H ^a   Han, S D ^a   Hong, C P ^a  

^a Daegu University   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMPUTATIONAL COMPLEXITY; DATA REDUCTION; DELAY CIRCUITS; DIGITAL SIGNAL PROCESSING; GRAPH THEORY; TIMING CIRCUITS; VLSI CIRCUITS;

CLOCK CYCLES; COMPUTATIONAL DELAY TIME; DIGIT SERIAL SYSTOLIC MULTIPLIER; FINITE FIELDS; HARDWARE COMPLEXITY;

MULTIPLYING CIRCUITS;

EID: 0034781735     PISSN: 10630988     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (13)

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2. m)
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4. Efficient semi-systolic architectures for finite field arithmetic
5. Digit-serial processing techniques
6. Systematic approach for design of digit-serial signal processing architectures
7. On supercomputing with systolic/wavefront array processors
8. A super-serial Galois fields multiplier for FPGAs and its application to public-key algorithms