A fast digit-serial systolic multiplier for finite field GF(2m)

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Volumn 2, Issue , 2005, Pages 1268-1271

  Kim, Chang Hoon ^a   Kwon, Soonhak ^b   Hong, Chun Pyo ^a  

^a Daegu University   (South Korea)

^b Sungkyunkwan University   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER AIDED DESIGN;

CLOCK CYCLES; CRITICAL PATHS; CRYPTOGRAPHIC APPLICATIONS; FINITE FIELDS; INNER STRUCTURE; PROPOSED ARCHITECTURES; SYSTOLIC MULTIPLIERS; VLSI IMPLEMENTATION;

TREES (MATHEMATICS);

EID: 77954751774     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1120725.1121040     Document Type: Conference Paper

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