VLSI implementation of bit-parallel word-serial multiplier in GF(22 33)

3rd International IEEE Northeast Workshop on Circuits and Systems Conference, NEWCAS 2005

Volumn 2005, Issue , 2005, Pages 399-402

  Tang, Wenkai ^a   Wu, Huapeng ^b   Ahmadi, Majid ^b  

^a Infineon Technologies   (China)

^b UNIVERSITY OF WINDSOR   (Canada)

Author keywords

[No Author keywords available]

Indexed keywords

BIT ERROR RATE; FINITE ELEMENT METHOD; FREQUENCY MULTIPLYING CIRCUITS; NETWORK PROTOCOLS; PUBLIC KEY CRYPTOGRAPHY; SMART CARDS;

BIT PARALLEL WORD SERIAL (BPWS); CRYPTOGRAPHIC PROCESSOR; FINITE FIELD MULTIPLIER; INTERNET PROTOCOL;

VLSI CIRCUITS;

EID: 33745796375     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

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