Digit-serial systolic multiplier for finite fields GF(2m)

IEE Proceedings: Computers and Digital Techniques

Volumn 145, Issue 2, 1998, Pages 143-148

  Guo, J H ^a   Wang, C L ^a  

^a NATIONAL TSING HUA UNIVERSITY   (Taiwan)

Author keywords

Digit serial architecture; Finite field multiplication; Standard basis; Systolic array; VLSI

Indexed keywords

COMPUTER ARCHITECTURE; DIGITAL ARITHMETIC; GRAPH THEORY; POLYNOMIALS; SYSTOLIC ARRAYS; TIMING CIRCUITS; VLSI CIRCUITS;

FINITE FIELD MULTIPLICATION;

MULTIPLYING CIRCUITS;

EID: 0032023469     PISSN: 13502387     EISSN: None     Source Type: Journal    
DOI: 10.1049/ip-cdt:19981906     Document Type: Article

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