Low complexity bit parallel architectures for polynomial basis multiplication over GF(2m)

IEEE Transactions on Computers

Volumn 53, Issue 8, 2004, Pages 945-959

  Reyhani Masoleh, Arash ^a   Hasan, M Anwar ^a  

^a UNIVERSITY OF WATERLOO   (Canada)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTATIONAL COMPLEXITY; COMPUTER ARCHITECTURE; COMPUTER HARDWARE; COMPUTER HARDWARE DESCRIPTION LANGUAGES; GRAPH THEORY; MATRIX ALGEBRA; OPTIMIZATION; PARALLEL PROCESSING SYSTEMS; POLYNOMIALS; THEOREM PROVING;

EQUALLY SPACED POLYNOMIALS; FINITE FIELD; GALOIS FIELD; MASTROVITO MULTIPLIER; PENTANOMIALS; POLYNOMIAL BASIS; REDUCTION MATRIX; TRINOMIALS;

DIGITAL ARITHMETIC;

EID: 3242725230     PISSN: 00189340     EISSN: None     Source Type: Journal    
DOI: 10.1109/TC.2004.47     Document Type: Article

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