FPGA implementation of an efficient multiplier over finite fields GF(2 m)

Proceedings - ReConFig 2005: 2005 International Conference on Reconfigurable Computing and FPGAs

Volumn 2005, Issue , 2005, Pages

  García Martínez, Mario Alberto ^a   Posada Gómez, Rubén ^a   Morales Luna, Guillermo ^b   Rodríguez Henríquez, Francisco ^b  

^a INSTITUTO TECNOLÓGICO DE ORIZABA   (Mexico)

^b DEPARTAMENTO DE FÍSICA   (Mexico)

Author keywords

[No Author keywords available]

Indexed keywords

ARITHMETIC OPERATIONS; FIELD MULTIPLICATION; FINITE FIELDS; SPACE COMPLEXITY;

CODES (SYMBOLS); COMPUTER SOFTWARE; CRYPTOGRAPHY; ERROR CORRECTION; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); MATHEMATICAL OPERATORS; SIGNAL PROCESSING;

FREQUENCY MULTIPLYING CIRCUITS;

EID: 33846957363     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/RECONFIG.2005.18     Document Type: Conference Paper

References (11)

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