Low-Energy Digit-Serial/Parallel Finite Field Multipliers

Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology

Volumn 19, Issue 2, 1998, Pages 149-166

  Song, Leilei ^a,b,c   Parhi, Keshab K ^a,d,e,f  

^a University of Minnesota   (United States)

^b NANKAI UNIVERSITY   (China)

^c UNIVERSITY OF MINNESOTA   (United States)

^d INDIAN INSTITUTE OF TECHNOLOGY   (India)

^e UNIVERSITY OF PENNSYLVANIA   (United States)

^f UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMPUTER ARCHITECTURE; PARALLEL PROCESSING SYSTEMS; POLYNOMIALS; CRYPTOGRAPHY; ENCODING (SYMBOLS); ERROR CORRECTION; ERROR DETECTION; INTEGRATED CIRCUIT LAYOUT; PARALLEL ALGORITHMS;

DIGIT-SERIAL/PARALLEL FINITE FIELD MULTIPLIERS;

MULTIPLYING CIRCUITS;

DIGIT SERIAL ARCHITECTURE; ERROR CONTROL CODES; PARALLEL FINITE FIELD MULTIPLIERS; PARALLEL MULTIPLICATION ALGORITHMS;

EID: 0032115233     PISSN: 13875485     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Article

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