Efficient semisystolic architectures for finite-field arithmetic

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 6, Issue 1, 1998, Pages 101-113

  Jain, Surendra K ^b   Song, Leilei ^a,b   Parhi, Keshab K ^a,b  

^a IEEE

^b University of Minnesota   (United States)

Author keywords

Cellular array; Exponentiator; Finite field; LSB first; MSB first; Multiplier; Polynomial basis; Power basis; Semisystolic; Squarer

Indexed keywords

ALGORITHMS; DIGITAL ARITHMETIC; INTEGRATED CIRCUIT LAYOUT; MULTIPLYING CIRCUITS; PIPELINE PROCESSING SYSTEMS; POLYNOMIALS; VLSI CIRCUITS;

FINITE FIELD ARITHMETIC; SUBSTRUCTURE SHARING;

SYSTOLIC ARRAYS;

EID: 0032023744     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/92.661252     Document Type: Article

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