A digit-serial multiplier for finite field GF(2m)

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 13, Issue 4, 2005, Pages 476-483

  Kim, Chang Hoon ^a   Hong, Chun Pyo ^a   Kwon, Soonhak ^b  

^a Daegu University   (South Korea)

^b Sungkyunkwan University   (South Korea)

Author keywords

Digit serial architecture; Finite field multiplication; Systolic array; VLSI

Indexed keywords

ALGORITHMS; DATA FLOW ANALYSIS; ERROR CORRECTION; GRAPH THEORY; POLYNOMIALS; VLSI CIRCUITS;

DIGIT-SERIAL ARCHITECTURE; DIGITAL-SERIAL MULTIPLIER; FINITE FIELD MULTIPLICATION; SYSTOLIC ARRAY;

COMPUTER ARCHITECTURE;

EID: 16444386466     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2004.842923     Document Type: Article

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