Formulation and validation of an energy dissipation model for the clock generation circuitry and distribution networks

Proceedings of the IEEE International Conference on VLSI Design

Volumn , Issue , 2001, Pages 248-253

  Duarte, D ^a   Narayanan, V ^a   Irwin, M J ^a   Kandemir, M ^a  

^a PENNSYLVANIA STATE UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CACHE MEMORY; CAPACITANCE; CMOS INTEGRATED CIRCUITS; ENERGY DISSIPATION; MOSFET DEVICES; OPTIMIZATION; TIMING CIRCUITS;

TRANSLATION LOOKASIDE BUFFER (TLB);

MICROPROCESSOR CHIPS;

EID: 0035007816     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (15)