Signal-path-level dual-Vt assignment for leakage power reduction

Journal of Circuits, Systems and Computers

Volumn 15, Issue 2, 2006, Pages 197-216

  Wang, Yu ^a   Yang, Huazhong ^a   Wang, Hui ^a  

^a TSINGHUA UNIVERSITY   (China)

Author keywords

Dual threshold voltage; Graph algorithm; Leakage power; Signal path level threshold voltage assignment; Static delay model

Indexed keywords

ALGORITHMS; CMOS INTEGRATED CIRCUITS; GATES (TRANSISTOR); MATHEMATICAL MODELS; NETWORKS (CIRCUITS); THRESHOLD VOLTAGE;

DUAL-THRESHOLD VOLTAGE; GRAPH ALGORITHM; LEAKAGE POWER; SIGNAL-PATH-LEVEL THRESHOLD VOLTAGE ASSIGNMENT; STATIC DELAY MODEL;

LEAKAGE CURRENTS;

EID: 33746878463     PISSN: 02181266     EISSN: None     Source Type: Journal    
DOI: 10.1142/S021812660600299X     Document Type: Article

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