Gate sizing and Vt assignment for active-mode leakage power reduction

Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors

Volumn , Issue , 2004, Pages 258-264

  Gao, Feng ^a   Hayes, John P ^a  

^a UNIVERSITY OF MICHIGAN   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BENCHMARKING; GATES (TRANSISTOR); HEURISTIC PROGRAMMING; INTEGRATED CIRCUITS; LINEAR PROGRAMMING; OPTIMIZATION; THRESHOLD VOLTAGE;

GATE SIZING; LEAKAGE POWER; POWER CONSUMPTION; POWER REDUCTION;

LEAKAGE CURRENTS;

EID: 17644375917     PISSN: 10636404     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (14)

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