A design approach for soft error protection in real-time embedded systems

Proceedings of the Australian Software Engineering Conference, ASWEC

Volumn , Issue , 2008, Pages 639-643

  Sadi, Muhammad Sheikh ^a   Myers, D G ^a   Sanchez, Cesar Ortega ^a  

^a CURTIN UNIVERSITY   (Australia)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC BREAKDOWN; EMBEDDED SYSTEMS; ERROR CORRECTION; ERRORS; INTEGRATED CIRCUITS; METAL RECOVERY; MICROPROCESSOR CHIPS; SEMICONDUCTOR DEVICE MANUFACTURE; SOFTWARE ENGINEERING; SPACE RESEARCH; TECHNOLOGY;

AUSTRALIAN SOFTWARE ENGINEERING CONFERENCE; DESIGN APPROACHES; DESIGN METHODOLOGIES; DESIGN SPACE EXPLORATION; LINE WIDTHS; REAL-TIME EMBEDDED SYSTEMS; SEMICONDUCTOR TECHNOLOGIES; SOFT ERROR PROTECTION; SOFT ERRORS; SYSTEM-ON-A-CHIP DESIGNS; SYSTEMS MODELLING;

REAL TIME SYSTEMS;

EID: 50249132460     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASWEC.2008.4483256     Document Type: Conference Paper

References (24)

1. J. C. Smolens, B. T. Gold, B. Falsafi, and J. C. Hoe, "Reunion: Complexity-Effective Multicore Redundancy," presented at 39th Annual IEEE/ACM International Symposium on Microarchitecture, MICRO-39, Dec 2006, pp. 223 - 234.
2. Z. Xinping and Q. Wei, "Prototyping a fault-tolerant multiprocessor SoC with run-time fault recovery," presented at 43rd ACM/IEEE Design Automation Conference , 24-28 July, 2006, pp. 53 - 56.
3. M. Zhang, "Analysis and design of soft-error tolerant circuits," Ph.D. Thesis, University of Illinois at UrbanaChampaign, United States - Illinois, 2006.
4. M. Zhang, S. Mitra, T. M. Mak, N. Seifert, N. J. Wang, Q. Shi, K. S. Kim, N. R. Shanbhag, and S. J. Patel, "Sequential Element Design With Built-in Soft Error Resilience," Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, vol. 14, no. 12, 2006, pp. 1368-1378.
5. M. Z. S. Mitra, N. Seifert, TM Mak and K. Kim. Soft and IFIP, "Soft Error Resilient System Design through Error Correction," VLSI-SoC, 2006.
6. S. S. Mukherjee, J. Emer, and S. K. Reinhardt, "The soft error problem: an architectural perspective," presented at 11th International Symposium on High-Performance Computer Architecture, San Francisco, CA, USA, 12-16 Feb., 2005, pp. 243 - 247.
7. J. M. Cazeaux, D. Rossi, M. Omana, C. Metra, and A. Chatterjee, "On transistor level gate sizing for increased robustness to transient faults," presented at 11th IEEE International On-Line Testing Symposium, 6-8 July, 2005, pp. 23-28.
8. S. Tosun, N. Mansouri, E. Arvas, M. Kandemir, and X. Yuan, "Reliability-centric high-level synthesis," presented at Proceedings Design, Automation and Test in Europe, 2005, pp. 1258-1263.
9. Y. Crouzet, J. Collet, and J. Arlat, "Mitigating soft errors to prevent a hard threat to dependable computing," presented at 11th IEEE International On-Line Testing Symposium, IOLTS, 2005, pp. 295-298.
10. S. Krishnamohan, "Efficient techniques for modeling and mitigation of soft errors in nanometer-scale static CMOS logic circuits," Ph.D. Thesis, Michigan State University, United States - Michigan, 2005.
11. M. W. Rashid, E. J. Tan, M. C. Huang, and D. H. Albonesi, "Power-efficient error tolerance in chip multiprocessors," Micro, IEEE, vol. 25, no. 6, 2005, pp. 60-70.
12. G. P. Saggese, N. J. Wang, Z. T. Kalbarczyk, S. J. Patel, and R. K. Iyer, "An experimental study of soft errors in microprocessors," Micro, IEEE, vol. 25, no. 6, 2005, pp. 30-39.
13. S. Borkar, "Designing reliable systems from unreliable components: the challenges of transistor variability and degradation," Micro, IEEE, vol. 25, no. 6, 2005, pp. 10-16.
14. P. J. Meaney, S. B. Swaney, P. N. Sanda, and L. Spainhower, "IBM z990 soft error detection and recovery," Device and Materials Reliability, IEEE Transactions on, vol. 5, no. 3, 2005, pp. 419-427.
15. S. Mitra, N. Seifert, M. Zhang, Q. Shi, and K. S. Kim, "Robust system design with built-in soft-error resilience," Computer, vol. 38, no. 2, 2005, pp. 43-52.
16. Y. Xie, L. Li, M. Kandemir, N. Vijaykrishnan, and M. J. Irwin, "Reliability-aware co-synthesis for embedded systems," presented at 15th IEEE International Conference on Application-Specific Systems, Architectures and Processors, 2004, pp. 41 - 50.
17. J. Srinivasan, S. V. Adve, P. Bose, and J. A. Rivers, "The case for lifetime reliability-aware microprocessors," presented at 31st Annual International Symposium on Computer Architecture, 19-23 June, 2004, pp. 276- 287.
18. N. A. Koso vets and L. N. Kosovets, "A fault-tolerant real-time multiprocessor with a built-in recovery mechanism," Cybernetics and Systems Analysis, vol. 40, no. 5, 2004, pp. 772.
19. A. G. Mohamed, S. Chad, T. N. Vijaykumar, and P. Irith, "Transient-fault recovery for chip multiprocessors," IEEE Micro, vol. 23, no. 6, 2003, pp. 76.
20. S. S. Mukherjee, M. Kontz, and S. K. Reinhardt, "Detailed design and evaluation of redundant multi-threading alternatives," presented at 29th Annual International Symposium on Computer Architecture, 2002, pp. 99-110.
21. T. N. Vijaykumar, I. Pomeranz, and K. Cheng, "Transient-fault recovery using simultaneous multithreading," presented at 29th Annual International Symposium on Computer Architecture, 2002, pp. 87-98.
22. J. Ray, J. C. Hoe, and B. Falsafi, "Dual use of superscalar datapath for transient-fault detection and recovery," presented at 34th ACM/IEEE International Symposium on Microarchitecture, 2001, pp. 214 - 224.
23. S. K. Reinhardt and S. S. Mukherjee, "Transient fault detection via simultaneous multithreading," presented at 27th International Symposium on Computer Architecture, 2000, pp. 25- 36.
24. T. M. Austin, "DIVA: a reliable substrate for deep submicron microarchitecture design," presented at 32nd Annual International Symposium on Microarchitecture, 1999, pp. 196-207.