Power-efficient error tolerance in chip multiprocessors

IEEE Micro

Volumn 25, Issue 6, 2005, Pages 60-70

  Rashid, M Wasiur ^a   Tan, Edwin J ^a   Huang, Michael C ^a,c   Albonesi, David H ^b  

^a UNIVERSITY OF ROCHESTER   (United States)

^b Cornell University ^*  (United States)

^c University of Rochester   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CHIP MULTIPROCESSORS; COMPUTATION THREAD; ERROR TOLERANCE;

COMPUTER ARCHITECTURE; ENERGY EFFICIENCY; ERROR ANALYSIS; FAULT TOLERANCE; MICROPROCESSOR CHIPS;

MULTIPROCESSING SYSTEMS;

EID: 34147151677     PISSN: 02721732     EISSN: None     Source Type: Journal    
DOI: 10.1109/MM.2005.118     Document Type: Article

References (15)

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