Prototyping a fault-tolerant multiprocessor SoC with run-time fault recovery

Proceedings - Design Automation Conference

Volumn , Issue , 2006, Pages 53-56

  Zhu, Xinping ^a   Qin, Wei ^b  

^a NORTHEASTERN UNIVERSITY   (United States)

^b BOSTON UNIVERSITY   (United States)

Author keywords

Fault tolerance; Multiprocessor system; Network on chip; Retargetable simulation; Run time verification; System on chip

Indexed keywords

COMPUTATION THEORY; COMPUTER SIMULATION; COMPUTER SOFTWARE; HARDWARE; INTEGRATED CIRCUITS; MULTIPROCESSING SYSTEMS; SILICON; SOFTWARE PROTOTYPING;

MULTIPROCESSOR SYSTEMS-ON-CHIPS (SOCS); RUN-TIME VERIFICATION; SINGLE PROGRAM, MULTIPLE DATA (SPMD); SYSTEMC; TOLERANTMULTIPROCESSOR SOC;

FAULT TOLERANCE;

EID: 34547149750     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1146909.1146926     Document Type: Conference Paper

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