메뉴 건너뛰기




Volumn , Issue , 2004, Pages 41-50

Reliability-aware co-synthesis for embedded systems

Author keywords

[No Author keywords available]

Indexed keywords

MEAN TIME BETWEEN FAILURES (MTBF); PROCESSING ELEMENTS (PE); SINGLE EVENT UPSET (SEU); TASK GRAPHS;

EID: 11244324452     PISSN: 10636862     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper
Times cited : (47)

References (15)
  • 1
    • 84860074327 scopus 로고    scopus 로고
    • http://www.embedded.com.au/market.html.
  • 5
    • 11244281606 scopus 로고    scopus 로고
    • Effects of neutrons on programmable logic
    • December
    • Actel Coroporation. Effects of neutrons on programmable logic, white paper, December 2002.
    • (2002) White Paper
  • 6
    • 0032666810 scopus 로고    scopus 로고
    • COFTA: Hardware-software co-synthesis of heterogeneous distributed embedded systems for low overhead fault tolerance
    • B. P. Dave and N. K. Jha. COFTA: Hardware-software co-synthesis of heterogeneous distributed embedded systems for low overhead fault tolerance. IEEE Transactions on Computers, 48(4):417-441, 1999.
    • (1999) IEEE Transactions on Computers , vol.48 , Issue.4 , pp. 417-441
    • Dave, B.P.1    Jha, N.K.2
  • 8
    • 0036082034 scopus 로고    scopus 로고
    • Soft error rate mitigation techniques for modern microcircuits
    • D. Mavis and P. Eaton. Soft error rate mitigation techniques for modern microcircuits. In Proceedings of Reliable Physics Symposium, pages 216-225, 2002.
    • (2002) Proceedings of Reliable Physics Symposium , pp. 216-225
    • Mavis, D.1    Eaton, P.2
  • 9
    • 0142184763 scopus 로고    scopus 로고
    • Cost-effective approach for reducing soft error failure rate in logic circuits
    • K. Mohanram and N. Touba. Cost-effective approach for reducing soft error failure rate in logic circuits. In Proceedings of International Test Conference, pages 893-901, 2003.
    • (2003) Proceedings of International Test Conference , pp. 893-901
    • Mohanram, K.1    Touba, N.2
  • 11
    • 51749085561 scopus 로고
    • A design methodology for the high-level synthesis of fault-tolerant ASICs
    • A. Orailoglu and R. Karri. A design methodology for the high-level synthesis of fault-tolerant ASICs. In VLSI Signal Processing V, pages 417-426, 1992.
    • (1992) VLSI Signal Processing V , pp. 417-426
    • Orailoglu, A.1    Karri, R.2
  • 15
    • 0029732375 scopus 로고    scopus 로고
    • IBM experiments in soft fails in computer electronics (1978-1994)
    • J. F. Ziegler. IBM experiments in soft fails in computer electronics (1978-1994). IBM Journal of Research and Development, 40(1):3-18, 1996.
    • (1996) IBM Journal of Research and Development , vol.40 , Issue.1 , pp. 3-18
    • Ziegler, J.F.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.