Towards a sub-2.5V, 100-Gb/s Serial Transceiver

Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, CICC 2007

Volumn , Issue , 2007, Pages 471-478

  Voinigescu, S P ^a   Aroca, R ^a   Dickson, T O ^a,b   Nicolson, S T ^a   Chalvatzis, T ^a   Chevalier, P ^c   Garcia, P ^c   Garnier, C ^c   Sautreuil, B ^c  

^a UNIVERSITY OF TORONTO   (Canada)

^b IBM T J WATSON RESEARCH CENTER   (United States)

^c STMICROELECTRONICS   (France)

Author keywords

[No Author keywords available]

Indexed keywords

BICMOS TECHNOLOGY; CLOCK DISTRIBUTION NETWORKS; ELECTRIC POWER DISTRIBUTION; FREQUENCY DIVIDING CIRCUITS; INTEGRATED CIRCUITS; SILICON ALLOYS; TRANSCEIVERS;

CRITICAL BLOCKS; LOW PHASE NOISE; NANO-SCALE CMOS; SIGE BICMOS PROCESS; SIGE BICMOS TECHNOLOGY; STATE OF THE ART; STATIC FREQUENCY DIVIDERS; TRANSFORMER MODELING;

SEMICONDUCTING SILICON;

EID: 49949104044     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/CICC.2007.4405776     Document Type: Conference Paper

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