A 165-Gb/s 4:1 multiplexer in InP DHBT technology

IEEE Journal of Solid-State Circuits

Volumn 41, Issue 10, 2006, Pages 2209-2213

  Hallin, Joakim ^b   Kjellberg, Torgil ^b   Swahn, Thomas ^a,b  

^a IEEE

^b CHALMERS UNIVERSITY OF TECHNOLOGY   (Sweden)

Author keywords

4:1 multiplexer; High speed digital circuit; InP DHBT

Indexed keywords

4:1 MULTIPLEXER; DATA SIGNALS; DOUBLE HETEROJUNCTION BIPOLAR TRANSISTOR (DHBT) TECHNOLOGY; HIGH-SPEED DIGITAL CIRCUITS;

DATA REDUCTION; HETEROJUNCTION BIPOLAR TRANSISTORS; SEMICONDUCTING INDIUM PHOSPHIDE; VOLTAGE CONTROL;

MULTIPLEXING;

EID: 33749512228     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2006.878114     Document Type: Conference Paper

References (13)

1. max over 300 GHz in a new manufacturable technology," IEEE Electron Device Lett., vol. 25, no. 8, pp. 520-522, Aug. 2004.
2. M. Le, G. He, R. Hess, P. Partyka, B. Li, R. Bryie, S. Rustomji, G. Kim, R. Lee, J. Pepper, M. Helix, R. Milano, R. Elder, D. Jansen, F. Stroili, J. Lai, and M. Feng, "Self-aligned InP DHBTs for 150 GHz digital and mixed signal circuits," in Proc. Indium Phosphide and Related Materials Conf., May 2005, pp. 325-330.
3. Z. Griffith, M. Dahlström, M. J. W. Rodwell, M. Urteaga, R. Pierson, P. Rowell, B. Brar, S. Lee, N. Nguyen, and C. Nguyen, "Ultra high frequency static dividers >150 GHz in a narrow mesa InGaAs/InP DHBT technology," in Proc. Bipolar/BiCMOS Circuits and Technology Meeting, Sep. 2004, pp. 176-179.
4. D. A. Hitko, T. Hussain, J. F. Jensen, Y. Royter, S. L. Morton, D. S. Matthews, R. D. Rajavel, I. Milosavljevlc, C. H. Fields, S. Thomas, III, A. Kurdoghllan, Z. Lao, K. Elliott, and M. Sokolich, "A low power (45mW/latch) static 150GHz CML divider," in Proc. IEEE Compound Semiconductor Integrated Circuit Symp., Oct. 2004, pp. 167-170.
5. M. Meghelli, "132-Gb/s 4:1 multiplexer in 0.13-μm SiGe-bipolar technology," IEEE J. Solid-State Circuits, vol. 39, no. 12, pp. 2403-2407, Dec. 2004.
6. K. Murata, K. Sano, H. Kitabayashi, S. Sugitani, H. Sugahara, and T. Enoki, "100-Gb/s multiplexing and demultiplexing IC operations in InP HEMT technology," IEEE J. Solid-State Circuits, vol. 39, no. 1, pp. 207-213, Jan. 2004.
7. Y. Suzuki, Z. Yamazaki, Y. Amamiya, S. Wada, H. Uchida, C. Kurioka, S. Tanaka, and H. Hida, "120-Ob/s multiplexing and 110-Gb/s demultiplexing ICs," IEEE J. Solid-State Circuits, vol. 39, no. 12, pp. 2397-2402, Dec. 2004.
8. T. Suzuki, Y. Nakasha, T. Takahashi, K. Makiyama, T. Hirose, and M. Takikawa, "144-Gbit/s selector and 100-Gbit/s 4:1 multiplexer using InP HEMTs," in IEEE MTT-S Int. Microwave Symp. Dig., Jun. 2004, pp. 117-120.
9. J. Hallin, T. Kjellberg, and T. Swahn, "A 165-Gb/s 4:1 multiplexer in InP DHBT technology," in Proc. IEEE Compound Semiconductor Integrated Circuit Symp., Nov. 2005, pp. 260-263.
10. A. Bechtel, M. Bennet, B. Booth, S. Crehan, and J. Goergen, "The need for 100G Ethernet?," in Proc. IEC DesignCon 2006, Management Forum Panel, Feb. 2006, Available: http://www.ethernetalliance.org.
11. 9 -1 PRB S generator in InP technology," in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, vol. 47, pp. 234-235, 525.
12. T. Swahn, J. Hallin, and T. Kjellberg, "Design and test of InP DHBT ICs for a 100 Gb/s demonstrator system," in Proc. Indium Phosphide, and Related Materials Conf., May 2006, pp. 79-84.
13. T. Suzuki, T. Takahashi, K. Makiyarna, K. Sawada, Y. Nakasha, T. Hirose, and M. Takikawa, "Under 0.5W 50Gb/s full-rate 4:1MUX and 1:4 DEMUX in 0.13 μm InP HEMT technology," in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, vol. 47, pp. 234-235, 525.