A 100-Gb/s 1:4 Demultiplexer in InP DHBT technology

Technical Digest - IEEE Compound Semiconductor Integrated Circuit Symposium, CSIC

Volumn , Issue , 2006, Pages 227-230

  Hallin, Joakim ^a   Kjellberg, Torgil ^a   Swahn, Thomas ^a  

^a CHALMERS UNIVERSITY OF TECHNOLOGY   (Sweden)

Author keywords

1:4 demultiplexer; High speed digital circuit; InP DHBT

Indexed keywords

ELECTRIC CONDUCTIVITY; INTEGRATED CIRCUITS; OPTICAL DESIGN; SEMICONDUCTOR MATERIALS;

(+ MOD 2N) OPERATION; 1:4 DEMULTIPLEXER; CLOCK ARCHITECTURE; COMPOUND SEMICONDUCTOR (CS); DEMULTIPLEXER; INP DHBT; MULTI-PHASE; PRBS GENERATORS; SUPPLY VOLTAGES;

DEMULTIPLEXING;

EID: 39549117924     PISSN: 15508781     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/CSICS.2006.319941     Document Type: Conference Paper

References (9)

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8. T. Swahn, J. Hallin, T. Kjellberg, "Design and test of InP DHBT ICs for a 100 Gb/s demonstrator system", Indium Phosphide and Related Materials Conference 2006, May 7-11 2006, To be published.
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