2D analysis of bottom gate misalignment and process tolerant for sub-100nm symmetric double-gate MOSFETs

2003 IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC 2003

Volumn , Issue , 2003, Pages 201-204

  Shen, Jian ^a   Man, Tsz Yin ^a   Chan, Mansun ^a  

^a HONG KONG UNIVERSITY OF SCIENCE AND TECHNOLOGY   (Hong Kong)

Author keywords

[No Author keywords available]

Indexed keywords

ALIGNMENT; ELECTRON DEVICES; SOLID STATE DEVICES;

2D ANALYSIS; PROCESS TOLERANT; PROCESS VARIATION; PUNCH-THROUGH; SINGLE GATES; SUBTHRESHOLD SWING; SYMMETRIC DOUBLE GATE; VERY DEEP SUB MICRONS;

MOSFET DEVICES;

EID: 84946404715     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/EDSSC.2003.1283514     Document Type: Conference Paper

References (4)

1. H.Y. Wong et al., "The Gate Misalignment Effects of the Sub-threshold Characteristics of sub-100nm DG-MOSFETs" 2002 HKEDM, pp91-95
2. F. Allibert et al., "Double-Gate MOSFETs: Is Gate Alignment Mandatory?" 2001 ESSDERC, pp267-70
3. TMA-MEDICI 4.0: Two-dimensional device simulation program: TMA, Inc.,1997
4. Y. Taur, "An Analytical Solution to a Double-Gate MOSFET with Undoped Body", EDL, May 2000, pp. 245-247