Statistical leakage and timing optimization for submicron process variation

Proceedings of the IEEE International Conference on VLSI Design

Volumn , Issue , 2007, Pages 439-444

  Lu, Yuanlin ^a   Agrawal, Vishwani D ^a  

^a AUBURN UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER PROGRAMMING LANGUAGES; DESIGN; INTEGER PROGRAMMING; INTEGRATED CIRCUITS; LEAKAGE CURRENTS; LINEARIZATION; TIME MEASUREMENT;

CIRCUIT DELAYS; DESIGN METHODS; DETERMINISTIC APPROACHES; DOPING CONCENTRATIONS; EFFECTIVE GATE LENGTHS; EXPONENTIAL RELATIONS; LEAKAGE POWER REDUCTIONS; LEAKAGE POWERS; MIXED-INTEGER LINEAR PROGRAMMINGS; OXIDE THICKNESSES; PROCESS PARAMETERS; PROCESS VARIATIONS; STATISTICAL APPROACHES; STATISTICAL LEAKAGES; SUB MICRONS; SUBTHRESHOLD CURRENTS; TIMING OPTIMIZATIONS; TOTAL POWER CONSUMPTIONS;

EMBEDDED SYSTEMS;

EID: 47649084398     PISSN: 10639667     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VLSID.2007.148     Document Type: Conference Paper

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