Input-specific dynamic power optimization for VLSI circuits

Proceedings of the International Symposium on Low Power Electronics and Design

Volumn 2006, Issue , 2006, Pages 232-237

  Hu, Fei ^a,c   Agrawal, Vishwani D ^b  

^a INTEL CORPORATION   (United States)

^b AUBURN UNIVERSITY   (United States)

^c AUBURN UNIVERSITY   (United States)

Author keywords

Dynamic power optimization; Glitch reduction; Input specific

Indexed keywords

COMPUTER SIMULATION; DELAY CIRCUITS; DIGITAL CIRCUITS; LINEAR PROGRAMMING; VECTORS;

DYNAMIC POWER OPTIMIZATION; GLITCH LESS DESIGN; POWER REDUCTION;

VLSI CIRCUITS;

EID: 34247184134     PISSN: 15334678     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1165573.1165630     Document Type: Conference Paper

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