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Volumn 3728 LNCS, Issue , 2005, Pages 217-226

Leakage and dynamic glitch power minimization using integer linear programming for vth, assignment and path balancing

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; INTEGER PROGRAMMING; LINEAR PROGRAMMING; MATHEMATICAL MODELS;

EID: 33646414454     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/11556930_23     Document Type: Conference Paper
Times cited : (4)

References (10)
  • 1
    • 0033885658 scopus 로고    scopus 로고
    • Low voltage low power CMOS design techniques for deep submicron ICs
    • L. Wei, K. Roy and V. K. De, "Low Voltage Low Power CMOS Design Techniques for Deep Submicron ICs," Proc. 13th International Conf. VLSI Design, 2000, pp. 24-29.
    • (2000) Proc. 13th International Conf. VLSI Design , pp. 24-29
    • Wei, L.1    Roy, K.2    De, K.V.3
  • 2
    • 0036907253 scopus 로고    scopus 로고
    • Standby power optimization via transistor sizing and dual threshold voltage assignment
    • M. Ketkar and S. S. Sapatnekar, "Standby Power Optimization via Transistor Sizing and Dual Threshold Voltage Assignment," Proc. ICCAD, 2002, pp. 375-378.
    • (2002) Proc. ICCAD , pp. 375-378
    • Ketkar, M.1    Sapatnekar, S.S.2
  • 3
    • 0031635596 scopus 로고    scopus 로고
    • Design and optimization of low voltage high performance dual threshold CMOS circuits
    • L. Wei, Z. Chen, M. Johnson and K. Roy, "Design and Optimization of Low Voltage High Performance Dual Threshold CMOS Circuits," Proc. DAC, 1998, pp. 489-494.
    • (1998) Proc. DAC , pp. 489-494
    • Wei, L.1    Chen, Z.2    Johnson, M.3    Roy, K.4
  • 4
    • 0032667127 scopus 로고    scopus 로고
    • Mixed-Vth (MVT) CMOS circuit design methodology for low power applications
    • L. Wei, Z. Chen, K. Roy, Y. Ye and V. De, "Mixed-Vth (MVT) CMOS Circuit Design Methodology for Low Power Applications," Proc. DAC, 1999, pp.430-435.
    • (1999) Proc. DAC , pp. 430-435
    • Wei, L.1    Chen, Z.2    Roy, K.3    Ye, Y.4    De, V.5
  • 5
    • 0032319165 scopus 로고    scopus 로고
    • Static power optimization of deep submicron CMOS circuits for dual VT technology
    • Q. Wang, and S. B. K. Vrudhula, "Static Power Optimization of Deep Submicron CMOS Circuits for Dual VT Technology," Proc, ICCAD, 1998, pp490-496.
    • (1998) Proc, ICCAD , pp. 490-496
    • Wang, Q.1    Vrudhula, S.B.K.2
  • 6
    • 1542359159 scopus 로고    scopus 로고
    • Minimization of dynamic and static power through joint assignment of threshold voltages and sizing optimization
    • D. Nguyen, A. Davare, M. Orshansky, D. Chinney, B. Thompson, and K. Keutzer, "Minimization of Dynamic and Static Power Through Joint Assignment of Threshold Voltages and Sizing Optimization," Proc. ISLPED, 2003, pp. 158-163.
    • (2003) Proc. ISLPED , pp. 158-163
    • Nguyen, D.1    Davare, A.2    Orshansky, M.3    Chinney, D.4    Thompson, B.5    Keutzer, K.6


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.