High performance dual-MAC DSP architecture

IEEE Signal Processing Magazine

Volumn 19, Issue 4, 2002, Pages 42-53

  Kolagotla, Ravi K ^a   Fridman, Jose ^b   Aldrich, Bradley C ^c   Hoffman, Marc M ^c   Anderson, William C ^c   Allen, Michael S ^c   Witt, David B ^c   Dunton, Randy R ^c   Booth Jr , Lawrence A ^c  

^a INTEL CORPORATION   (United States)

^b IEEE

^c IEEE Design and Implementation of Signal Processing Systems ^*

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; BANDWIDTH; BUFFER STORAGE; DECISION MAKING; EQUALIZERS; MICROCONTROLLERS; MOTION ESTIMATION; PROGRAM ASSEMBLERS; SHIFT REGISTERS;

MICRO SIGNAL ARCHITECTURES (MSA);

DIGITAL SIGNAL PROCESSING;

EID: 85032751343     PISSN: 10535888     EISSN: None     Source Type: Journal    
DOI: 10.1109/MSP.2002.1012349     Document Type: Article

References (5)

1. Implementing the Viterbi algorithm