Algorithmic complexity, motion estimation and a VLSI architecture for MPEG-4 core profile video codecs

International Symposium on VLSI Technology, Systems, and Applications, Proceedings

Volumn , Issue , 2001, Pages 172-175

  Stechele, W ^a  

^a TECHNICAL UNIVERSITY OF MUNICH   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; APPLICATION SPECIFIC INTEGRATED CIRCUITS; COMPUTER SOFTWARE; DATA FLOW ANALYSIS; DATA STORAGE EQUIPMENT; EMBEDDED SYSTEMS; IMAGE CODING; MOTION ESTIMATION; REDUCED INSTRUCTION SET COMPUTING; STATISTICAL METHODS;

BITSTREAM PROCESSING; VIDEO CODECS; VLSI ARCHITECTURE;

VLSI CIRCUITS;

EID: 0034842719     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (10)

1. Design trends in multimedia hardware architectures
2. Complexity analysis of the emerging MPEG-4 standard as a basis for VLSI implementation
3. Motion compensated interframe coding for video conferencing
4. The MPEG-4 multimedia coding standard: Algorithms, architectures and applications