Test directive generation for functional coverage closure using inductive logic programming

Proceedings - IEEE International High-Level Design Validation and Test Workshop, HLDVT

Volumn , Issue , 2006, Pages 11-18

  Hsueh, Hsiou Wen ^a   Eder, Kerstin ^a  

^a UNIVERSITY OF BRISTOL   (United Kingdom)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER PROGRAMMING; FUNCTIONAL PROGRAMMING; LAWS AND LEGISLATION; LOGIC PROGRAMMING; MICROPROCESSOR CHIPS; PROCESS DESIGN; PROCESS ENGINEERING; TELECOMMUNICATION NETWORKS;

CASE STUDIES; COVERAGE ANALYSIS; COVERAGE DRIVEN VERIFICATION (CDV); DESIGN PROCESSES; FUNCTIONAL COVERAGE; FUNCTIONAL VERIFICATIONS; GENERAL (CO); HIGH LEVEL DESIGNS; INDUCTIVE LEARNING; INDUCTIVE LOGIC PROGRAMMING (ILP); INTERNATIONAL (CO); NOVE L APPROACH; RULE LEARNING; TARGET COVERAGE; TEST GENERATIONS; TIME CONSUMING TASKS;

TESTING;

EID: 46249123691     PISSN: 15526674     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/HLDVT.2006.320005     Document Type: Conference Paper

References (20)

1. A. Adir, E. Almog, L. Fournier, E. Marcus, M. Rimon, M. Vinov, and A. Ziv. Genesys-Pro: Innovations in test program generation for functional processor verification. IEEE Design A Test of Computers, 21(2):84-93, March-April 2004.
2. M Bose, J. Shin, E. M. Rudnick. T Dukes, and M. Abadir. A genetic approach to automatic bias generation for biased random instruction generation. In CEC2001: Congress on Evolutionary Computing, pages 442-448, May 2001.
3. M. Btaun, S. Fine, and A. Ziv, Enhancing the Efficiency of Bayesian Network Based Coverage Directed Test Generation. In IEEE Internalinal High-level Validation and Test Workshop (HLDT), 2004.
4. F. Corno. G. Cumani, M. S. Reorda. and G. Squillero. Evolutionary test program induction for microprocessor design verification. In ATS2002: IEEE Asian Test Symposium, pages 368-373. Guam (USA). November 2002.
5. F. Corno, G. Cumani, M. S. Reorda, and G. Squillero. Fully automatic test program generation for microprocessor cores. In DATE2003: Design, Automation and Test in Europe, pages 1006-1011. Munich (Germany), March 3-7 2003.
6. S. Fine and A. Ziv. Coverage directed test generation for functional verification using Bayesian networks. In DAC2003: 40th Design Automation Conference, pages 286-291. Anaheim, California (USA), June 2003.
7. S. Fine and A. Ziv. Enhancing the control and efficiency of the covering process. In HLDVT2003: High-level Design Verification and Test Workshop. IEEE, 2003.
8. P. Finn, S. Muggleton, D. Page, and A. Srinivasan. Pharmacophore Discovery using the Inductive Logic Programming System PROGOL. Machine Learning, 30:241-273, 1998.
9. I Horch. Entwurf eines RISC-Prozessors in der Hardwarebeschreibungssprache VHDL. Technical report, TU Darmstadt Institut für Datentechnik, 1997.
10. A. K. Jain. M. N. Murty, and P. J. Flynn. Data clustering: A review. ACM Computing Surveys, 31(3):264-323. September 1999.
11. R. D. King, K. E. Whelan, E M. Jones, P. G. K. Reiser, C. H. Bryant, S. H. Muggleton. D. B. Kell, and S, G. Oliver. Functional genomic hypothesis generation and experimentation by a robot scientist. Nature, 427:247-251, January 2004.
12. O. I.achish, E. Marcus, S. Ur, and A. Ziv. Hole analysis for functional coverage data. In DAC2002: 39th Design Automation (conference, New Orleans, Louisiana (USA). June 2002.
13. N. Lavrac and S. Dzeroski. Inductive Logic Progamming. Techniques and Applications. Ellis Horwood, New York. 1994.
14. J. W. Lloyd. Foundations of Logic Programming. Springer-Verlag. second, extended edition, 1987.
15. S. Muggleton. Inverse Entailment and Progol. New Generation Computing, 13(3-4):245-286, 1995.
16. G. Nativ, S Mitteniwier, S. Ur. and A. Ziv Cost evaluation of coverage directed test generation for the IBM mainframe. In ITC2001: International Test Conference, pages 793--802, October 2001.
17. D. Page and A. Srinivasan. ILP: A shon look back and a longer look forward. Journal of Machine Learning Research. 4:415-430, 2003.
18. J. Smith, M. Bartley, and T, Fogarty. Microprocessor design verification by two-phase evolution of variable length tests. In Proceedings of the 1997 IEEE International Conference on Evolutionary Computing, pages 453-458. IEHK Press, 1997.
19. S. Tasiran and K. Keutzer. Coverage metrics for functional validation of hardware designs. IEEE Design & Test of Computers, 18(4):36-45, 2001.
20. I. Wagner, V. Bertacco, and T. Austin. StressTest: An automatic approach to test generation via activity monitors. In DAC2005: 42nd Design Automation Conference, pages 783-788, Anaheim, California (USA). June 2005.