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Volumn 21, Issue 2, 2004, Pages 84-93

Genesys-Pro: Innovations in test program generation for functional processor verification

Author keywords

[No Author keywords available]

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; CONSTRAINT THEORY; DESIGN FOR TESTABILITY; MICROPROCESSOR CHIPS; REQUIREMENTS ENGINEERING; VERY LONG INSTRUCTION WORD ARCHITECTURE;

EID: 1942436273     PISSN: 07407475     EISSN: None     Source Type: Journal    
DOI: 10.1109/MDT.2004.1277900     Document Type: Article
Times cited : (140)

References (16)
  • 2
    • 0034840742 scopus 로고    scopus 로고
    • Validating the intel pentium 4 microprocessor
    • ACM Press
    • B. Bentley, "Validating the Intel Pentium 4 Microprocessor," Proc. 38th Design Automation Conf. (DAC 01), ACM Press, 2001, pp. 244-248.
    • (2001) Proc. 38th Design Automation Conf. (DAC 01) , pp. 244-248
    • Bentley, B.1
  • 3
    • 0031639694 scopus 로고    scopus 로고
    • Functional verification of a multiple-issue, out-of-order, superscalar alpha processor - The DEC alpha 21264 microprocessor
    • ACM Press
    • S. Taylor et al., "Functional Verification of a Multiple-Issue, Out-of-Order, Superscalar Alpha Processor - the DEC Alpha 21264 Microprocessor," Proc. 35th Design Automation Conf. (DAC 98), ACM Press, 1998, pp. 638-643.
    • (1998) Proc. 35th Design Automation Conf. (DAC 98) , pp. 638-643
    • Taylor, S.1
  • 5
    • 0001909165 scopus 로고    scopus 로고
    • Functional verification methodology for microprocessors using the genesys test program generator: Application to the x86 microprocessors family
    • IEEE CS Press
    • L. Fournier, Y. Arbetman, and M. Levinger, "Functional Verification Methodology for Microprocessors Using the Genesys Test Program Generator: Application to the x86 Microprocessors Family," Proc. Design Automation and Test in Europe (DATE99), IEEE CS Press, 1999, pp. 434-441.
    • (1999) Proc. Design Automation and Test in Europe (DATE99) , pp. 434-441
    • Fournier, L.1    Arbetman, Y.2    Levinger, M.3
  • 6
    • 0001314320 scopus 로고
    • Verification of the IBM RISC system/6000 by a dynamic biased pseudo-random test program generator
    • Apr.
    • A. Aharon et al., "Verification of the IBM RISC System/6000 by a Dynamic Biased Pseudo-random Test Program Generator," IBM System J., vol. 30, no. 4, Apr. 1991, pp. 527-538.
    • (1991) IBM System J. , vol.30 , Issue.4 , pp. 527-538
    • Aharon, A.1
  • 8
    • 0036991699 scopus 로고    scopus 로고
    • Using constraint satisfaction formulations and solution techniques for random test program generation
    • Aug.
    • E. Bin et al., "Using Constraint Satisfaction Formulations and Solution Techniques for Random Test Program Generation," IBM Systems J., vol. 41, no. 3, Aug. 2002, pp. 386-402.
    • (2002) IBM Systems J. , vol.41 , Issue.3 , pp. 386-402
    • Bin, E.1
  • 9
    • 4444315783 scopus 로고    scopus 로고
    • Industrial experience with test generation languages for processor verification
    • M. Behm et al., "Industrial Experience with Test Generation Languages for Processor Verification," submitted to DAC 04, 2004.
    • DAC 04, 2004
    • Behm, M.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.