Hole analysis for functional coverage data

Proceedings - Design Automation Conference

Volumn , Issue , 2002, Pages 807-812

  Lachish, Oded ^a   Marcus, Eitan ^a   Ur, Shmuel ^a   Ziv, Avi ^a  

^a UNIVERSITY OF HAIFA   (Israel)

Author keywords

Coverage analysis; Functional verification

Indexed keywords

COVERAGE ANALYSIS; FUNCTIONAL VERIFICATION;

COMPUTER AIDED SOFTWARE ENGINEERING; INFORMATION ANALYSIS; INTEGRATED CIRCUIT TESTING; PROGRAM PROCESSORS;

DATA PROCESSING;

EID: 0036047838     PISSN: 0738100X     EISSN: None     Source Type: Journal    
DOI: 10.1109/DAC.2002.1012733     Document Type: Article

References (13)

1. Test program generation for functional verification of PowerPC processors in IBM
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3. The Pentium bug, an industry watershed
4. Functional verification methodology for microprocessors using the Genesys test-program generator
5. User defined coverage - A tool supported methodology for design verification
6. High quality behavioral verification using statistical stopping criteria
7. The map method for synthesis of combinational logic circuits
8. Inductions of decision trees
9. Off-the-shelf vs. custom made coverage models, which is the one for you?