StressTest: An automatic approach to test generation via activity monitors

Proceedings - Design Automation Conference

Volumn , Issue , 2005, Pages 783-788

  Wagner, Ilya ^a   Bertacco, Valeria ^a   Austin, Todd ^a  

^a UNIVERSITY OF MICHIGAN   (United States)

Author keywords

Architectural simulation; Directed random simulation; High performance simulation

Indexed keywords

CLOSED LOOP CONTROL SYSTEMS; COMPUTER SIMULATION; MARKETING; MICROPROCESSOR CHIPS; SYSTEMS ANALYSIS;

ARCHITECTURAL SIMULATION; DIRECTED-RANDOM SIMULATION; HIGH-PERFORMANCE SIMULATION;

COMPUTER ARCHITECTURE;

EID: 27944434994     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/dac.2005.193922     Document Type: Conference Paper

References (12)

1. Constrained-random test generation and functional coverage with Vera. Technical report, Synopsys, Inc, Feb. 2003.
2. Specman elite - testbench automation, 2004. http://www.verisity.com/ products/specman.html.
3. A. Allan, D. Edenfeld, W. H. Joyner, Jr., A. B. Kahng, M. Rodgers, and Y. Zorian. 2001 technology roadmap for semiconductors. IEEE Computer, pages 42-53, Jan. 2002.
4. M. Behm, J. Ludden, Y. Lichtenstein, M. Rimon, and M. Vinov. Industrial experience with test generation languages for processor verification. DAC 2004, June 2004.
5. B. Bentley. Validating the Intel Pentium 4 microprocessor. In DAC, Proceedings of Design Automation Conference, pages 224-228, 2001.
6. E.A.Poe. Introduction to random test generation for processor verification. Technical report, Obsidian Software, 2002.
7. S. Fine and A. Ziv. Coverage directed test generation for functional verification using bayesian networks. In DAC, Proceedings of Design Automation Conference, pages 286-281, June 2003.
8. Y. Levhari. Verification of the PalmDSPCore using pseudo random techniques. Technical report, VeriSure Consulting, Ltd., 2002.
9. J. M. Ludden et.al. Functional verification of the POWER4 microprocessor and POWER4 multiprocessor systems. IBM Journal of Research and Development, 46:53-76, Jan. 2002.
10. I. Silas, I. Frumkin, E. Hazan, E. Mor, and G. Zobin. System-level validation of the Intel Pentium M processor. Intel Technology Journal, 07:38-43, May 2003.
11. S. Tasiran, F. Fallah, D. G. Chinnery, S. J. Weber, and K. Keutzer. A functional validation technique: Biased-random simulation guided by observability-based coverage. ICCD, Proceedings of the International Conference on Computer Design, pages 82-88, 2001.
12. S. Taylor, M. Quinn, D. Brown, N. Dohm, S. Hildebrandt, J. Huggins, and C. Ramey. Functional verification of a multiple-issue, out-of-order, superscalar Alpha processor: The DEC Alpha 21264 microprocessor. In DAC, Proceedings of Design Automation Conference, pages 638-644, 1998.