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Volumn , Issue , 2006, Pages

Transaction monitoring in networks on chip: The on-chip run-time perspective

Author keywords

[No Author keywords available]

Indexed keywords

ABSTRACTION LEVELS; AREA COST; EXPERIMENTAL SET UPS; MONITOR (CO); MULTIPROCESSOR SYSTEMS-ON-CHIP (MPSOC); NETWORKS ON CHIP (NOCS); ON CHIPS; RUN TIME; RUN TIME ANALYSIS; TRANSACTION LEVEL; TRANSPORT DATA;

EID: 46149123009     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IES.2006.357464     Document Type: Conference Paper
Times cited : (41)

References (22)
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  • 4
    • 1242309790 scopus 로고    scopus 로고
    • QNoC: QoS architecture and design process for network on chip
    • Feb, Special issue on Networks on Chip
    • E. Bolotin, I. Cidon, R. Ginosar, and A. Kolodny. QNoC: QoS architecture and design process for network on chip. Journal of Systems Architecture, 50(2-3): 105-128, Feb. 2004. Special issue on Networks on Chip.
    • (2004) Journal of Systems Architecture , vol.50 , Issue.2-3 , pp. 105-128
    • Bolotin, E.1    Cidon, I.2    Ginosar, R.3    Kolodny, A.4
  • 5
    • 33745183091 scopus 로고    scopus 로고
    • C. Ciordas, T. Basten, A. Rǎdulescu, K. Goossens, and J. van Meerbergen. An event-based monitoring service for networks on chip. ACM Transactions on Design Automation of Electronic Systems, 10(4):702-723, Oct. 2005. HLDVT'04 Special Issue on Validation of Large Systems.
    • C. Ciordas, T. Basten, A. Rǎdulescu, K. Goossens, and J. van Meerbergen. An event-based monitoring service for networks on chip. ACM Transactions on Design Automation of Electronic Systems, 10(4):702-723, Oct. 2005. HLDVT'04 Special Issue on Validation of Large Systems.
  • 8
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    • Route packets, not wires: Onchip interconnection networks
    • ACM
    • W. J. Dally and B. Towles. Route packets, not wires: onchip interconnection networks. In Proc. Design Automation Conference (DAC), pages 684-689, 2001, ACM 2001.
    • (2001) Proc. Design Automation Conference (DAC) , pp. 684-689
    • Dally, W.J.1    Towles, B.2
  • 11
    • 27344456043 scopus 로고    scopus 로고
    • The Æthereal network on chip: Concepts, architectures, and implementations
    • Sept-Oct
    • K. Goossens, J. Dielissen, and A. Rǎdulescu. The Æthereal network on chip: Concepts, architectures, and implementations. IEEE Design and Test of Computers, 22(5):21-31, Sept-Oct 2005.
    • (2005) IEEE Design and Test of Computers , vol.22 , Issue.5 , pp. 21-31
    • Goossens, K.1    Dielissen, J.2    Rǎdulescu, A.3
  • 13
    • 0036760592 scopus 로고    scopus 로고
    • An interconnect architecture for networking systems on chips
    • Sept
    • F. Karim, A. Nguyen, and S. Dey. An interconnect architecture for networking systems on chips. IEEE Micro, 22(5):36-45, Sept. 2002.
    • (2002) IEEE Micro , vol.22 , Issue.5 , pp. 36-45
    • Karim, F.1    Nguyen, A.2    Dey, S.3
  • 15
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    • An embedded debugging architecture for socs
    • Feb-March
    • R. Leatherman and N. Stollon. An embedded debugging architecture for socs. IEEE Potentials, 24(1): 12-16, Feb-March 2005.
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  • 21
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  • 22
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    • Bringing communication networks on chip: Test and verification implications
    • Sept
    • B. Vermeulen, J. Dielissen, K. Goossens, and C. Ciordas. Bringing communication networks on chip: Test and verification implications. IEEE Communications Magazine, 41(9):74-81, Sept. 2003.
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.