Cell architecture for nanoelectronic design

Microelectronics Journal

Volumn 39, Issue 8, 2008, Pages 1041-1050

  Martorell, Ferran ^a   Rubio, Antonio ^a  

^a UNIVERSITAT POLITÈCNICA DE CATALUNYA   (Spain)

Author keywords

Averaging cell; Defect tolerance; Fault tolerance; Nanoarchitecture

Indexed keywords

ARCHITECTURE; CELLS; DEFECT STRUCTURES; NANOSTRUCTURED MATERIALS; NANOTECHNOLOGY; OPTICAL DESIGN; PROBABILITY; STANDARDS;

CELL ARCHITECTURES; DESIGN CIRCUITS; ELSEVIER (CO); ERROR PROBABILITIES; ERROR TOLERANCE (ET); FABRICATION DEFECTS; GATE LEVELS; IMPLEMENTATION COMPLEXITY; INTERNAL NOISE; NAND GATES; NANO SCALING; NANO-DEVICES; NANO-SCALE DEVICES; NANOCIRCUITS; NANOELECTRONIC; NANOTECHNOLOGY RESEARCH; NOISE MARGIN (NM); OUTPUT RESPONSE; PARAMETER VARIABILITY; PARAMETER VARIATIONS; STANDARD DEVIATION (STD);

ARCHITECTURAL DESIGN;

EID: 46149097379     PISSN: 00262692     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.mejo.2007.10.008     Document Type: Article

References (25)

1. Kish L. Moore's law and the energy requirement of computing versus performance. IEE Proc. Circuits Devices Syst. 151 2 (2004) 190-194
2. International technology roadmap for semiconductors, ITRS, 〈http://www.itrs.net/Common/2005ITRS/Home2005.htm〉, 2005.
3. Kleinosowski A., Pai V., Rangarajan V., Ranganath P., Kleinosowski K., Subramony M., and Lilja D. Exploring fine-grained fault tolerance for nanotechnology devices with the recursive nanobox processor grid. IEEE Trans. Nanotechnol. 5 (2006) 575-586
4. von Neumann J. Probabilistic logics and the synthesis of reliable organisms from unreliable components. In: Shannon C., and McCarthy J. (Eds). Automata Studies (1955), Princeton University Press, Princeton, NJ 43-98
5. Strukov D.B., and Likharev K.K. CMOL FPGA: a reconfigurable architecture for hybrid digital circuits with two-terminal nanodevices. Nanotechnology 16 6 (2005) 888-900
6. Snider G., Kuekes P., and Williams R. CMOS-like logic in defective, nanoscale crossbars. Nanotechnology 15 (2004) 881-891
7. DeHon A. Deterministic addressing of nanoscale devices assembled at sublithographic pitches. IEEE Trans. Nanotechnol. 4 (2005) 681-687
8. Sadek A.S., Nikolic K., and Forshaw M. Parallel information and computation with restitution for noise-tolerant nanoscale logic networks. Nanotechnology 15 1 (2004) 192-210
9. Roy S., and Beiu V. Majority multiplexing-economical redundant fault-tolerant designs for nanoarchitectures. IEEE Trans. Nanotechnol. 4 (2005) 441-451
10. Nikolic K., Sadek A., and Forshaw M. Fault-tolerant techniques for nanocomputers. Nanotechnology 13 (2002) 357-362
11. Stan M.R., Franzon P.D., Goldstein S.C., Lach J.C., and Ziegler M.M. Molecular electronics: from devices and interconnect to circuits and architecture. Proc. IEEE 91 11 (2003) 1940-1957
12. Martorell F., Cotofana S.D., and Rubio A. Fault tolerant structures for nanoscale gates. Proceedings of the Seventh IEEE International Conference on Nanotechnology (2007) 605-610
13. Lorczak P., Caglayan A., and Eckhardt D. A theoretical investigation of generalised voters. Proceedings of FTCS'19: IEEE 19th Annual International Symposium on Fault-Tolerant Computing Systems. Chicago (1989) 444-451
14. Parhami B. IEEE Trans. Reliab. 40 3 (1991) 380-394
15. Schmid A., and Leblebici Y. Robust circuit and system design methodologies for nanometer-scale devices and single-electron transistors. IEEE Trans. VLSI Syst. 12 (2004) 1156-1166
16. Chen J., Reed M., Rawlett A., and Tour J. Large on-off ratios and negative differential resistance in a molecular electronic device. Science 286 (1999) 1550-1552
17. Hoenlein W., Kreupl F., Duesberg G., Graham A., Liebau M., Seidel R., and Unger E. Carbon nanotube applications in microelectronics. IEEE Trans. Components Packag. Technologies 27 4 (2004) 629-634
18. J. Lerch, Threshold gate circuits employing field-effect transistors, U.S. Patent 3715603.
19. In: Waser R. (Ed). Nanoelectronics and Information Technology: Advanced Electronic Materials and Novel Devices (2003), Wiley-VCH, Berlin
20. F. Martorell, S. Cotofana, A. Rubio, Modeling the fluctuations sources effects on the nanogate reliability, Internal Report, 〈http://pmos.upc.es/blues/publications/NanoReliability.pdf〉, 2007.
21. Rao R., Devgan A., Blaauw D., and Sylvester D. Analytical yield prediction considering leakage/performance correlation. IEEE Trans. Comput.-Aided Des. Integrated Circuits Syst. 25 (2006) 1685-1695
22. Cotofana S.D., Schmid A., Leblebici Y., Ionescu A., Soffke O., Zipf P., Glesner M., and Rubio A. CONAN-a design exploration framework for reliable nano-electronics architectures. Proceedings of the 16th International Conference on Application-Specific Systems, Architectures and Processors (2005) 260-267
23. Muroga S. Threshold Logic and its Applications (1971), Wiley, New York
24. Salman H., Soen Y., and Braun E. Voltage fluctuations and collective effects in ion-channel protein ensembles. Phys. Rev. Lett. 77 21 (1996) 4458-4461
25. Ising E. Beitrag zur theorie des ferromagnetismus. Z. Phys. 31 (1925) 253-258