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Volumn , Issue , 2005, Pages 260-267

CONAN - A design exploration framework for reliable nano-electronics architectures

Author keywords

[No Author keywords available]

Indexed keywords

CONSTRAINT THEORY; ELECTRIC POWER UTILIZATION; FAULT TOLERANT COMPUTER SYSTEMS; MATHEMATICAL MODELS; RELIABILITY;

EID: 24944438414     PISSN: 10636862     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper
Times cited : (14)

References (22)
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  • 4
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  • 5
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    • Defect and error tolerance in the presence of massive number of defects
    • May-June
    • M.A. Breuer, S.K. Gupta and T.M. Mak, "Defect and error tolerance in the presence of massive number of defects", IEEE Design and Test of Computers, May-June 2004, pp. 216-227.
    • (2004) IEEE Design and Test of Computers , pp. 216-227
    • Breuer, M.A.1    Gupta, S.K.2    Mak, T.M.3
  • 7
    • 3042583169 scopus 로고    scopus 로고
    • Understanding yield losses in logic circuits
    • May-June
    • D. Appelle et al., "Understanding yield losses in logic circuits", IEEE Design and Test of Computers, May-June 2004, pp. 208-215.
    • (2004) IEEE Design and Test of Computers , pp. 208-215
    • Appelle, D.1
  • 8
    • 0043065549 scopus 로고    scopus 로고
    • The future of nanocomputing
    • August
    • G. Bourianoff, "The future of nanocomputing", IEEE Computer, August 2003, pp. 44-53.
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    • Bourianoff, G.1
  • 9
    • 0023979062 scopus 로고
    • Reliable computation by formulas in the presence of noise
    • March
    • N. Pippenger, "Reliable computation by formulas in the presence of noise", IEEE Tr. on Information Theory, March 1988, pp. 194-197.
    • (1988) IEEE Tr. on Information Theory , pp. 194-197
    • Pippenger, N.1
  • 10
    • 0032510985 scopus 로고    scopus 로고
    • A defect tolerant computer architecture: Opportunities for nanotechnology
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    • Heath, J.R.1
  • 11
    • 2942750315 scopus 로고    scopus 로고
    • Single electron encoded latches and flip-flops
    • June
    • C. Lageweg et al., "Single Electron Encoded Latches and Flip-Flops", IEEE Transactions on Nanotechnology, vol. 3, no. 2, June 2004.
    • (2004) IEEE Transactions on Nanotechnology , vol.3 , Issue.2
    • Lageweg, C.1
  • 14
    • 2942720952 scopus 로고    scopus 로고
    • Hybrid CMOS-SET architecture with coulomb Bbockade oscillations and high current drive
    • June
    • A.M. Ionescu, S. Mahapatra, V. Pott, "Hybrid CMOS-SET Architecture with Coulomb Blockade Oscillations and High Current Drive", IEEE Electron Device Letters (EDL), Volume: 25, Issue: 6, pp.411-413, June 2004.
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    • Ionescu, A.M.1    Mahapatra, S.2    Pott, V.3
  • 18
    • 9244230573 scopus 로고    scopus 로고
    • Robust circuit and system design methodologies for nanometer-scale devices and single-electron transistors
    • accepted for publication in the, Nov.
    • A. Schmid and Y. Leblebici, "Robust Circuit and System Design Methodologies for Nanometer-Scale Devices and Single-Electron Transistors,"accepted for publication in the Special Issue on Nanoelectronics - IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 12, no. 11, pp.1156-1166, Nov. 2004.
    • (2004) Special Issue on Nanoelectronics - IEEE Transactions on Very Large Scale Integration (VLSI) Systems , vol.12 , Issue.11 , pp. 1156-1166
    • Schmid, A.1    Leblebici, Y.2
  • 20
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  • 21
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    • M. M. Ziegler, M. R. Stan, "CMOS/Nano Co-Design for Crossbar-Based Molecular Electronic Systems,"Proc. IEEE Nanotechnology, vol. 2, no. 4, December 2004, pp. 217-230.
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  • 22
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    • Array of nanometer-scale devices performing logic operations with fault-tolerant capability
    • München, Germany, August
    • A. Schmid and Y. Leblebici, "Array of Nanometer-Scale Devices Performing Logic Operations with Fault-Tolerant Capability,"Fourth IEEE Conference on Nanotechnology IEEE-NANO, München, Germany, August 2004.
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    • Schmid, A.1    Leblebici, Y.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.