A new scan partition scheme for low-power embedded system

ETRI Journal

Volumn 30, Issue 3, 2008, Pages 412-420

  Kim, Hong Sik ^a   Kim, Cheong Ghil ^b   Kang, Sungho ^a  

^a Yonsei University   (South Korea)

^b Namseoul University   (South Korea)

Author keywords

Design for testability; Power dissipation; Scan partitioning; Scan testing; Test cube

Indexed keywords

DESIGN FOR TESTABILITY; EMBEDDED SYSTEMS; ENERGY DISSIPATION; GRAPHIC METHODS; SCANNING; TESTING;

BENCHMARK CIRCUIT; LOW POWER EMBEDDED SYSTEMS; PROPOSED ARCHITECTURES; SCAN PARTITIONING; SCAN TESTING; SCAN-BASED TESTING; SWITCHING ACTIVITIES; TEST CUBE;

ELECTRIC LOSSES;

EID: 45949106307     PISSN: 12256463     EISSN: None     Source Type: Journal    
DOI: 10.4218/etrij.08.0107.0092     Document Type: Article

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