A novel scan architecture for power-efficient, rapid test

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers

Volumn , Issue , 2002, Pages 299-303

  Sinanoglu, Ozgur ^a   Orailoglu, Alex ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

SCAN BASED TEST; TEST RESPONSE DATA;

ELECTRIC POWER SUPPLIES TO APPARATUS; FAILURE ANALYSIS; INTEGRATED CIRCUIT LAYOUT; LOGIC DESIGN; SEQUENTIAL CIRCUITS; VECTORS;

INTEGRATED CIRCUIT TESTING;

EID: 0036911433     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/774572.774617     Document Type: Conference Paper

References (11)

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11. H. K. Lee and D. S. Ha, On the Generation of Test Patterns for Combinational Circuits, Technical Report 12-93, Department of Electrical Eng., Virginia Polytechnic Institute and State University.